Eishi Morimatsu

Development of a VLSI chip set for H.261/MPEG-1 video codec

A VLSI chip set fully compatible with both CCITT/H.261 and ISO/MPEG-1 has been developed. The chip set is composed of 3 chips, MC-LSI, COD-LSI, and DEC-LSI which realize a realtime coding of moving pictures based on the international standard coding algorithms. A realtime decoder can also be realized by single use of a DEC-LSI chip. Each chip includes 140,000 to 160,000 gates using 0.8 micrometers CMOS technology and operates at 27 MHz clock rate. The chip set performs full frame coding/decoding of CIF and SIF, and operates up to 6.3 Mb/s in the transmission bitrate. The chip set has been installed into a prototype video codec controlled by a PC(FM-TOWNS) and confirmed to work successfully.

Development of a VLSI chip for real time MPEG-2 video decoder

A VLSI chip fully compatible with ISO/IEC 13818 2 (MPEG-2 video) has been developed. The chip is conforming to main profile @ main level of the standard, which realizes real-time decoding of ITU-R Rec.601 format moving pictures. In addition, it is also designed to operate as a part of MPEG-2 encoder. The chip size and power dissipation are minimized by optimizing its architecture and by using hardware macro cells for bulky circuits such as multipliers. As a result, the chip has been implemented with approximately 620K transistors on 11.35/spl times/11.35 mm using a triple metal 0.5 /spl mu/m CMOS technology. The chip has performed well in evaluations on a PC-based testbed.