Kiichi Matsuda

Development of a VLSI chip set for H.261/MPEG-1 video codec

A VLSI chip set fully compatible with both CCITT/H.261 and ISO/MPEG-1 has been developed. The chip set is composed of 3 chips, MC-LSI, COD-LSI, and DEC-LSI which realize a realtime coding of moving pictures based on the international standard coding algorithms. A realtime decoder can also be realized by single use of a DEC-LSI chip. Each chip includes 140,000 to 160,000 gates using 0.8 micrometers CMOS technology and operates at 27 MHz clock rate. The chip set performs full frame coding/decoding of CIF and SIF, and operates up to 6.3 Mb/s in the transmission bitrate. The chip set has been installed into a prototype video codec controlled by a PC(FM-TOWNS) and confirmed to work successfully.

Variable bit rate HDTV communication in ATM networks

Variable bit rate high-definition-television (HDTV) communication in asynchronous-transfer-mode (ATM) networks is discussed. Terminal functions required for support of variable-bit-rate HDTV communication are outlined. Detection of lost and misdelivered cells, handling of cell delay variation, source clock frequency recovery, and segmentation and reassembly of user information are shown to be adaptation layer requisites. Multimedia multiplexing, virtual channel control, and required network quality for multimedia communication are also discussed. Adaptation functions for intrafield adaptive differential pulse-code modulation coding are described, and an experimental HDTV codec and an ATM terminal adapter are presented.<<ETX>>

A compact 100-160 Mb/s HDTV DPCM-AQ codec

A compact and economical HDTV (high-definition TV) codec is described. It employs DPCM (differential pulse code modulation)-based variable-length coding and transmits 1125/60 HDTV signals at rates from 100 to 160 Mb/s. DPCM-AQ (adaptive quantization) with variable-length codes was employed to achieve ease of hardware structure and required picture quality for distribution services. Performance evaluation showed that a satisfactory picture quality was obtained for practical use, even at a 100 Mb/s transmission rate, with only a slightly perceptible resolution loss in complex textures.<<ETX>>

A Realization Of MC/DCT By Video Signal Processors

One type of video signal processors is introduced in this paper, for which multi-processor configuration and required operations are studied. The hybrid coding scheme of MC/DCT is noted as an algorithm of high efficiency for low bit rate coding. But it has a problem that the decoded pictures of receiver are spoilt if the calculation types of inverse-DCT are not identical in transmitter and receiver. So two approaches of DC coefficient separation and conversion of the transfer range on the block by block basis are taken to solve this IDCT mismatch problem by improving the precision of IDCT calculation. To decide the transfer range, three methods are studied. The computer simulation is done to prove the performance of these methods, and the application of the processor is also studied to each method.

High efficiency 64 kb/s video codec based on a hybrid quantization

The authors discuss an experimental 64-kb/s video codec that transmits still and motion pictures in several coding modes. In previous work (1986), they proposed a coding scheme, tailored to 384-kb/s transmission, that used motion-compensated prediction and hybrid quantization and a 64-kb/s video codec design concept having several coding modes. Here, they detail the computer simulation used to check the proposed coding, schemes efficiency at 64 kb/s. They then describe the hardware architecture that implements the design concept. The performance of the video codec is then demonstrated in different coding modes.<<ETX>>