Eitan Marcus

Constraint-based random stimuli generation for hardware verification

We report on random stimuli generation for hardware verification at IBM as a major applica-tion of various artificial intelligence technologies, including knowledge representation, expert systems, and constraint satisfaction. For more than a decade we have developed several related tools, with huge payoffs. Research and development around this application are still thriving, as we continue to cope with the ever-increasing complexity of modern hardware systems and demanding business environments.

Hole analysis for functional coverage data

One of the main goals of coverage tools is to provide the user with informative presentation of coverage information. Specifically, information on large, cohesive sets of uncovered tasks with common properties is very useful. This paper describes methods for discovering and reporting large uncovered spaces (holes) for cross-product functional coverage models. Hole analysis is a presentation method for coverage data that is both succinct and informative. Using case studies, we show how hole analysis was used to detect large uncovered spaces and improve the quality of verification.

Defining coverage views to improve functional coverage analysis

Coverage analysis is used to monitor the quality of the verification process. Reports provided by coverage tools help users identify areas in the design that have not been adequately tested. Because of their sheer size, the analysis of large coverage models can be an intimitating and time-consuming task. Practically, it can only be done 6y focusing on specific parts of the model. This paper presents a method for defining views onto the coverage data of cross-product functional coverage models. The proposed method allows users to focus on cenain aspects of the coverage data to extract relevant, useful infonnation, thereby improving the quality of the coverage analysis. A number of examples are provided that show how the proposed method improved the verification of actual designs.

Adaptive test program generation: planning for the unplanned

Simulation of automatically-generated test programs is the primary means for verifying complex hardware designs and random test program generators therefore play a major role in the verification process of micro-processors. The input for a test program generator is typically an abstract specification-a template-of the tests to be generated. Due to randomness, generators often encounter situations that were not anticipated when the test specification was written. We introduce the concept of adaptive test program generation, which is designed to handle these unforeseen situations. We propose a technique that defines unexpected events together with their alternative program specifications. When an event is detected, its corresponding alternative specification is injected into the test program.

Improving test quality through resource reallocation

Test program generation typically involves the resolution of constraints to make the tests legal and interesting for verification. This is often achieved through the values of resources used by the instructions in the test. The difficulty is that the number of available resources is limited, and there may be fewer available resources than needed values (especially in long tests). One way to get a large number of values from a limited number of resources, is to insert value-assigning instructions into the test before the instruction that is to use the resources value. We refer to this as resource reloading. This paper presents a reloading technique that minimizes the interference caused. by the reloading instructions and avoids fixed code patterns by distancing the reloading instruction from the instruction that uses the resource value. The basic technique is presented along with several useful extensions and is compared with other reloading approaches.

Enhancing Scenario Quality Using Quasi-Events

A major challenge for processor-level stimuli generators is the need to generate stimuli that exercise deep micro-architectural mechanisms. Advanced generators address this challenge by applying expert testing knowledge that bias the stimuli toward interesting verification events. In this paper, we present a new approach whereby scenarios are not just enhanced, but are actually modified by testing knowledge. By allowing such mutations, scenarios are diverted toward quasi-events that are semantically related, though not identical, to the original intent of the scenario. We describe the importance of quasi-events and the usefulness of automated scenario mutations for improving the verification of speculative execution.

An ontology and constraint based approach to cache preloading

The verification of modern microprocessor-based systems requires stressing the cache hierarchy and effectively covering its huge state space. Cache hierarchy initialization (or preloading) is a technique that enables simulation to start from a rich, complex system-level setup, thereby simplifying the task of dynamically driving the hierarchy into the required corner cases. In this paper we introduce CacheLoader, a new, design-independent cache-preloading technology. The tools architecture follows the principles of ontology-based software to achieve complete separation between the cache-preloading engine and design dependent knowledge. Constraint satisfaction techniques are used to generate valid, interesting system initialization, and to satisfy explicit user directives. CacheLoader is currently being used by verification teams of several large scale designs in IBM. Results show that this technique provides superior coverage and user controllability, speeds up the construction of mature verification environments, simplifies maintenance, encourages encapsulation of domain knowledge, and enables reuse across verification environments and cache hierarchy designs.