Hesham F. A. Hamed

Low-Power Tunable Analog Circuit Blocks Based on Nanoscale Double-Gate MOSFETs

We illustrate unique examples of low-power tunable analog circuits built using independently driven nanoscale DG-MOSFETs, where the top gate response is altered by application of a control voltage on the bottom gate. In particular, we provide examples for a single-ended CMOS amplifier pair, a Schmitt trigger circuit and a operational transconductance amplifier C filter, circuit blocks essential for low-noise high-performance integrated circuits for analog and mixed-signal applications. The topologies and biasing schemes explored here show how the nanoscale DG-MOSFETs may be used for efficient, tolerant and smaller circuits with tunable characteristics.

High performance wideband CMOS current conveyor for low voltage low power applications

New low voltage low power CMOS current conveyor (CCII) is presented. The proposed CCII is based on rail-to-rail class AB folded cascode operational amplifier. The new CCII provides very low input impedance at X-port, very high input impedance at Y-port, accurate voltage and current tracking with low offset, and very wide bandwidth. As an application, an oscillator has been built based on the proposed CCII. The performance of the proposed CCII has been confirmed by PSPICE simulation program using TSMC MOSIS 0.18 µm CMOS technology. The presented CCII is supplied at ± 0.75 V.

Small size third order coupled resonator band-pass filter using capacitor loaded slots

In this paper, we present a small size third order band pass coupled resonator filter. The filter consists of defected ground structure resonators (DGSs). The reduction of the size is achieved by loading the resonator with lumped capacitor. The insertion of lumped capacitor within resonator increases the effective capacitance and reduces the resonant frequency, so the dimensions of the filter will reduce and the performance of the filter will improve by enhancing the energy stored in the resonator. A third order band pass filter with center frequency of 2.4GHZ with single transmission zero at 2.61 GHz is designed and simulated. The filter has pass band from 2.3 to 2.52 GHz and wide stop band with rejection higher than 20dB up to more than 8GHZ, and insertion loss lower than 1 dB is achieved within pass band.

Low-Power Tuneable Analog Circuit Blocks Based on Nanoscale Dual-Gate MOSFETs

We illustrate unique examples of low-power tunable analog circuits built using independently driven nano-scale DG-MOSFETs, where the top gate response is altered by application of a control voltage on the bottom gate. In particular, we provide examples for a single-ended CMOS amplifier pair, a Schmitt Trigger circuit and a OTA-C filter, circuit blocks essential for low-noise high-performance integrated circuits for analog applications. The topologies and biasing schemes explored here show how the nanoscale DG-MOSFETs may pave way for efficient, tolerant and smaller circuits with tunable characteristics.

1 V supply second generation current conveyor in standard CMOS technology for low voltage low power analog circuits applications

Second generation current conveyor (CCII) in standard CMOS technology for low voltage, low power analog circuits applications are presented. The main features of the proposed CMOS CCII are, it can operate at low voltage supply (1V), consume low power (383 muW), low input resistance at X-terminal (Rx = 6.9ohm), at low biasing current (16muA), low offset voltage (1.3mV), wide band width (F-3dB = 82MHz), and is very simple in its structure. As applications for proposed CCII, a four quadrant analog multiplier was built. PSPICE is used to verify the performance of the circuits

Low voltage low power highly linear CCIIs and its applications

In this paper, low voltage low power highly linear second-generation current conveyor (CCII) is presented. The proposed circuits are capable of operating at low voltage supply (/spl plusmn/1V), with reduced power consumption (in range of uW). PSPICE simulations results show that the -3 dB bandwidth extends beyond 138 MHz and linear voltage relation between X terminal, and Y terminal. The proposed CCIIs has many useful applications especially for low voltage low power analog filters.

High Throughput Asynchronous NoC Design under High Process Variation

Asynchronous switching is proposed as a robust design to mitigate the impact of process variation in Network on Chip (NoC). Circuit analysis is used to evaluate the influence of process variation on both synchronous and asynchronous designs. The impact of process variation is evaluated on different NoC topologies. Network on chip interconnects and clock distribution network are considered under process variation with the advance in technology. The variation in logic and interconnect are included to evaluate the delay, throughput and leakage power variation with different NoC topologies. In addition, the delay and throughput variation are evaluated for clock distribution network. For asynchronous NoC design, the throughput negligibly decreases under high process variation conditions in different NoC topologies. The throughput variation for synchronous design in all topologies rapidly decreases by up to 25% at the same variation conditions. Synchronous and asynchronous designes are provided for NoC.The throughput of synchronous design rapidly reduces as compared to nominal values for different technologies.The throughput of asynchronous designe under process variation almost remains the same as compared to nominal values for different topologies

Gain and bandwidth improvement of microstrip patch antenna using Complementary G-Shape Split Ring Resonator

In this paper, a periodic structure of Complementary G-Shape Split Ring Resonator (CGSRR) is proposed to improve the gain of microstrip patch antenna (MPA). CGSRR is designed to work as a left-handed material (LHM) with negative permittivity and permeability in the frequency band of operation. The MPA is designed with 50 Ω co-axial probe feed to operate at frequency f0=10 GHZ. Array of CGSRRs are loaded around the rectangular patch to improve the gain and bandwidth of the MPA. The presence of the CGSRRs around the patch antenna improves the gain by 2.5 dB over the original values of the total gain of the conventional antenna. CGSRR also increases the fractional bandwidth of the antenna from 3.5% to 5.1%. The proposed antenna is implemented and fabricated by the method of photolithography process. Experimental results are presented to show the performance of the antenna. The experimental results agree well with the simulation ones.

Advanced Encryption Standard Algorithm: Issues and Implementation Aspects

Data encryption has become a crucial need for almost all data transaction application due to the large diversity of the remote information exchange. A huge value of sensitive data is transferred daily via different channels such as e-commerce, electronic banking and even over simple email applications. Advanced Encryption Standard (AES) algorithm has become the optimum choice for various security services in numerous applications. Therefore, many researches get focused on that algorithm in order to improve its efficiency and performance. This paper presents a survey about the cutting edge research conducted for the AES algorithm issues and aspects in terms of developments, implementations and evaluations. The contribution of this paper is targeted toward building a base for future development and implementation of the AES algorithm. It also opens door for implementing the AES algorithm using some machine learning techniques.

New ± 0.75 V low voltage low power CMOS current conveyor

In this paper a new low voltage low power class AB CMOS second generation current conveyor (CCII) based on Rail-to-Rail folded cascode Op-Amp is presented, with a great performance. The proposed CCII provides very low input impedance at X-port, very high input impedance at Y-port, accurate voltage and current tracking with low offset, and wide bandwidth. As an application, a four quadrant analog multiplier has been built based on the proposed CCII. The proposed CCII performance has been investigated by Pspice simulation program using TSMC 0.18 µm CMOS technology. The presented CCII is supplied at ± 0.75 V.