Eliezer Halpern

Direct measurement of surface states density and energy distribution in individual InAs nanowires

InAs nanowires are candidates for future high-speed electronic and optoelectronic applications due to their high electron mobility and large coherence length. However, InAs surfaces are known to possess a high concentration of donor-type surface states, which results in an electron accumulation layer and, consequently, Fermi level pinning. Since the surface to volume ratio in nanowires is very large, the effect of surface states is greatly enhanced. We present a method for directly determining the density and energy distribution of single nanowire surface states using Kelvin probe force microscopy measured on a nanowire field-effect transistor and interpreted by electrostatic modeling. Here, the method is applied to individual InAs nanowires, which similarly to bulk InAs exhibit a prominent accumulation layer consisting of a large concentration of donor-type surface states. Nevertheless, due to the small diameter of the nanowires, the electron accumulation and Fermi level pinning take place within the ent...

Reconstruction of Surface Potential from Kelvin Probe Force Microscopy Images

We present an algorithm for reconstructing a sample surface potential from its Kelvin probe force microscopy (KPFM) image. The measured KPFM image is a weighted average of the surface potential underneath the tip apex due to the long-range electrostatic forces. We model the KPFM measurement by a linear shift-invariant system where the impulse response is the point spread function (PSF). By calculating the PSF of the KPFM probe (tip+cantilever) and using the measured noise statistics, we deconvolve the measured KPFM image to obtain the surface potential of the sample.The reconstruction algorithm is applied to measurements of CdS-PbS nanorods measured in amplitude modulation KPFM (AM-KPFM) and to graphene layers measured in frequency modulation KPFM (FM-KPFM). We show that in the AM-KPFM measurements the averaging effect is substantial, whereas in the FM-KPFM measurements the averaging effect is negligible.

Room Temperature Observation of Quantum Confinement in Single InAs Nanowires

Quantized conductance in nanowires can be observed at low temperature in transport measurements; however, the observation of sub-bands at room temperature is challenging due to temperature broadening. So far, conduction band splitting at room temperature has not been observed in III-V nanowires mainly due to the small energetic separations between the sub-bands. We report on the measurement of conduction sub-bands at room temperature, in single InAs nanowires, using Kelvin probe force microscopy. This method does not rely on charge transport but rather on measurement of the nanowire Fermi level position as carriers are injected into a single nanowire transistor. As there is no charge transport, electron scattering is no longer an issue, allowing the observation of the sub-bands at room temperature. We measure the energy of the sub-bands in nanowires with two different diameters, and obtain excellent agreement with theoretical calculations based on an empirical tight-binding model.

Surface chemical modification induces nanometer scale electron confinement in field effect device

Design, preparation, and study of physicochemical properties of molecular assemblies are extremely challenging multidisciplinary research fields. Understanding the elementary principles that correlate these properties with molecular level of electronic behavior will enable us to control basic properties of molecule-based compounds as well as of classical semiconductors. In particular, chemical modification of field effect sensor devices where the metal gate is replaced with organic molecular layer, projects a crucial impact upon the electrical properties of the sensor. In these cases it is important to control the effects in order to ensure that the organic gate is optimized for sensing. Here we used fully depleted silicon-on-insulator (SOI) ion sensitive field effect transistor in order to analyze the projection of surface chemical modification on electronic performance. We suggest that surface activation and the application of 3-aminopropyltrimethoxysilane on top of the gate dielectric introduces negative charge at the Si/SiO(2) interface or/and on top of the gate dielectric and consequently an accumulation layer that confines the electrons to the bottom of the SOI channel. The transistor gain postmodification is characteristic of volume inversion, and therefore suggests that, following modification, the channel electrons are confined to SOI thickness of <10 nm. Finally, measurements of pH sensitivity indicate that the pH sensitivity post-UV/O(3) treatment is maximized suggesting that the negative charge is introduced during the activation process, where the density of the negatively charged amphoteric sites maximized.

Sub-harmonic wireless injection locking of a THz CMOS chip array

A novel concept is introduced for generating high power frequency locked THz radiating based on CMOS chips. The concept is based on an array of CMOS VCO chips with on-chip ring antennas. With fundamental mm-wave oscillation around 115 GHz, the 3rd harmonic of 0.35 THz is radiated with record total radiated power (TRP) of -4.3 dBm, EIRP of +3.8 dBm, DC-to-THz efficiency of 1.4% and phase noise better than -95 dBc/Hz at 10 MHz offset. Using a buffer-less Colpitts topology both improves the output power and efficiency but also allows wireless locking of the VCO fundamental frequency using the on-chip antenna, which is an RF-choke for that frequency. This allows wireless coupling between array CMOS chip elements integrated on-board for mutual locking and also wireless locking to an external D-band reference. The concept is demonstrated using a 1×4 array of CMOS radiating chips. The sources can be tuned from 343 to 347 GHz and the injection locking range is around 80 MHz. The 1×4 array has an EIRP of +13.8 dBm, a TRP and DC-to-THz efficiency of +1 dBm and 1.2%, respectively. The 1×4 array locked signal follows the phase noise of the external reference (+9.5 dB) up to a locking range around 80 MHz. This new concept enables simple and cost effective locked CMOS THz scalable source arrays.

20.4 A 300GHz wirelessly locked 2×3 array radiating 5.4dBm with 5.1% DC-to-RF efficiency in 65nm CMOS

CMOS technology innovations over the last decades opened doors to the possibility of designing fully integrated systems in CMOS at THz frequencies. Small antenna sizes at THz frequencies make CMOS and silicon attractive for steerable 2D transmitter and receiver arrays. Previous works successfully showed THz-source arrays with the use of on-chip antennas [1-5]. However, it is still a challenge implementing such arrays that are frequency and phase locked, with significant radiated power and efficiency in standard CMOS without costly additions. In this work we propose a scalable radiating-transmitter approach in 65nm CMOS that achieves a radiated power of +5.4dBm at 0.3THz using only a 2×3 on-chip array, an EIRP of +22dBm and 5.1% of radiated-power-to-DC power efficiency.

An on-chip active frequency multiplier-by-seven (X-band to W-band) for millimeter-wave signal generation

This paper discusses an active on-chip multiplier for mm-wave generation, implemented in CMOS 65nm TSMC technology. The multiplying is done within single stage, which is connected via wire bonds to 4 stage PA, reducing the DC power consumption to 360 mW, 80 mW for the multiplying stage and 280 mW for the PA. Total core silicon area of 0.92 mm2, 0.31 mm2 the multiplier area and 0.61 mm2 the PA area. Achieving Psat of 6 dBm at 82 GHz.