Eran Socher

Pull-in study of an electrostatic torsion microactuator

Pull-in study of an electrostatic microactuator is essential for making the electrostatic actuation more effective. In this paper, pull-in analysis is presented for an electrostatic torsion microactuator. The torsion microactuator can be used as a microtorsion mirror. A polynomial algebraic equation for the pull-in voltage and pull-in angle of a torsion microactuator is derived. Two types of microactuators fabricated using bulk micromachining are presented. Measurements done on the fabricated microactuators are reported, showing deviations within 1% error from the calculations.

CMP network-on-chip overlaid with multi-band RF-interconnect

In this paper, we explore the use of multi-band radio frequency interconnect (or RF-I) with signal propagation at the speed of light to provide shortcuts in a many core network-on-chip (NoC) mesh topology. We investigate the costs associated with this technology, and examine the latency and bandwidth benefits that it can provide. Assuming a 400 mm2 die, we demonstrate that in exchange for 0.13% of area overhead on the active layer, RF-I can provide an average 13% (max 18%) boost in application performance, corresponding to an average 22% (max 24%) reduction in packet latency. We observe that RF access points may become traffic bottlenecks when many packets try to use the RF at once, and conclude by proposing strategies that adapt RF-I utilization at runtime to actively combat this congestion.

Power reduction of CMP communication networks via RF-interconnects

As chip multiprocessors scale to a greater number of processing cores, on-chip interconnection networks will experience dramatic increases in both bandwidth demand and power dissipation. Fortunately, promising gains can be realized via integration of radio frequency interconnect (RF-I) through on-chip transmission lines with traditional interconnects implemented with RC wires. While prior work has considered the latency advantage of RF-I, we demonstrate three further advantages of RF-I: (1) RF-I bandwidth can be flexibly allocated to provide an adaptive NoC, (2) RF-I can enable a dramatic power and area reduction by simplification of NoC topology, and (3) RF-I provides natural and efficient support for multicast. In this paper, we propose a novel interconnect design, exploiting dynamic RF-I bandwidth allocation to realize a reconfigurable network-on-chip architecture. We find that our adaptive RF-I architecture on top of a mesh with 4B links can even outperform the baseline with 16B mesh links by about 1%, and reduces NoC power by approximately 65% including the overhead incurred for supporting RF-I.

RF interconnects for communications on-chip

In this paper, we propose a new way of implementing on-chip global interconnect that would meet stringent challenges of core-to-core communications in latency, data rate, and re-configurability for future chip-microprocessors (CMP) with efficient area and energy overheads. We discuss the limitation of traditional RC-limited interconnects and possible benefits of multi-band RF-interconnect (RF-I) through on-chip differential transmission lines. The physical implementation of RF-I and its projected performance versus overhead as the function of CMOS technology scaling are discussed as well

Millimeter-wave CMOS digital controlled artificial dielectric differential mode transmission lines for reconfigurable ICs

Digital control of the effective dielectric constant of a differential mode transmission line is shown up to 60GHz in standard CMOS technology. The effective dielectric constant is shown to increase from 5 to over 50 for the fixed artificial dielectric case. The digital controlled artificial dielectric transmission line (DiCAD) uses MOS switches to dynamically control the phase. DiCAD achieves 50% of the physically available tuning range with effective dielectric constants varying between 7 and 28. Measured results favorably agree with full-wave electromagnetic simulations.

On the Effect of Residual Charges on the Pull-In Parameters of Electrostatic Actuators

In this paper a quantitative model for the effect of residual-charge upon the Pull-In parameters of electrostatic actuators is presented. The model is derived for a general electrostatic actuator with a charge sheet located arbitrarily in a dielectric coating layer. The main interesting new results derived from the model are: (i) the pull-in displacement is unaffected by the residual-charge and the travel range is only extended due to the series dielectric capacitor, (ii) the pull-in voltage is significantly reduced due to the residual charge, independent of the residual charge polarity.

A 210–227 GHz Transmitter With Integrated On-Chip Antenna in 90 nm CMOS Technology

This paper presents a transmitter operating in the 210-227 GHz in 90 nm CMOS, based on a Colpitts VCO. The third harmonic of the generated VCO fundamental signal is coupled to an on-chip dipole antenna. A simplified model is presented for the operation and the design of the circuit, which compares well with simulated and measured results. The transmitter achieves an EIRP of +1.8 dBm at 217 GHz and directivity of about +10 dBi. The circuit consumes 128 mW of DC power and an area of 0.53 mm2.

Analysis and design of an X -band-to- W -band CMOS active multiplier with improved harmonic rejection

Third-harmonic current generation in a CMOS transistor is modeled and analyzed including the effects of large-signal clipping and high-frequency roll-off for the application of millimeter-wave (mm-wave) frequency multipliers. Using the model and introducing harmonic rejection techniques, a wideband 8.5-dBm output-power x9 frequency multiplier from X-band to W-band implemented using a 65-nm CMOS process is designed and characterized. Six transformer coupled differential stages are used, two tripler stages, a Ka-band amplifier, and a three-stage W-band power amplifier (PA). The circuit reaches a saturated output power of 8.5 dBm at 91.8 GHz with a 12.2% bandwidth from 88 to 99.5 GHz. Excellent suppression of unwanted harmonics is achieved with better than 31 dBc across all bandwidth. The core design occupies only 390 μm × 675 μm and consumes 438 mW from a 1.2-/2.4-V supply.

A Dual-Band Millimeter-Wave CMOS Oscillator With Left-Handed Resonator

A new technique using a left-handed (LH) resonator to generate a multiband millimeter-wave carrier signal is proposed in this paper. The LH resonator exhibits nonlinear dispersion characteristic, which enables uneven spacing between resonant frequencies. With N stages of the LH unit cell, there are N/2 +1 resonant frequencies from the nonlinear dispersion curve. Moreover, the band selection switches are not located in the signal path, which can, therefore, dramatically reduce the size of switches and improve the overall quality factor of the resonator. A dual-band millimeter-wave oscillator in digital 90-nm CMOS technology is implemented to demonstrate this new technique. Using a mode selection switch, the proposed oscillator operates at 21.3 and 55.3 GHz, respectively, with a total power consumption of 14 mW.

Temperature sensitivity of SOI-CMOS transistors for use in uncooled thermal sensing

The temperature coefficient of current (TCC) of CMOS transistors implemented on silicon-on-insulator substrates is theoretically and empirically studied for its potential use in uncooled thermal sensing. Modeling and measurements show TCC values in subthreshold of more than 6%/K, better than state of the art microbolometer temperature coefficient of resistance, and less than -0.4%/K in saturation-comparable with metals. Models and measurements are shown for the TCC dependence upon operating point, temperature and channel length. A simple semi-empirical model for the TCC at subthreshold based on long channel approximation is suggested and shown to agree with measurements for channel length down to 0.35 /spl mu/m. The model and measurements show a logarithmic tradeoff between subthreshold current and the TCC, which is important in the design of sensors.