Samuel Jameson

A 210–227 GHz Transmitter With Integrated On-Chip Antenna in 90 nm CMOS Technology

This paper presents a transmitter operating in the 210-227 GHz in 90 nm CMOS, based on a Colpitts VCO. The third harmonic of the generated VCO fundamental signal is coupled to an on-chip dipole antenna. A simplified model is presented for the operation and the design of the circuit, which compares well with simulated and measured results. The transmitter achieves an EIRP of +1.8 dBm at 217 GHz and directivity of about +10 dBi. The circuit consumes 128 mW of DC power and an area of 0.53 mm2.

High Efficiency 293 GHz Radiating Source in 65 nm CMOS

This letter presents a J-band radiating source (284-301 GHz) based on a differential Colpitts oscillator with an on-chip antenna in 65 nm CMOS. The source radiates the third harmonic of the oscillation frequency, which is also generated in the voltage controlled oscillator (VCO) itself due to its large voltage signal. An integrated loop antenna serves also as the load inductance at the drains of the VCO transistors, acting as a choke at the fundamental and matched antenna at the third harmonic. The antenna has a directivity above +9 dBi across the tuning range. This frequency source has a DC-to-RF radiated power efficiency of 2.8%, a radiated power of -2.7 dBm and an EIRP of +6.4 dBm, taking a silicon area of only 0.26 mm2.

A Low-Power Low-Cost 24 GHz RFID Tag With a C-Flash Based Embedded Memory

The key factor in widespread adoption of Radio Frequency Identification (RFID) technology is tag cost minimization. This paper presents the first low-cost, ultra-low power, passive RFID tag, fully integrated on a single substrate in a standard CMOS process. The system combines a 24 GHz, dual on-chip antenna, RF front-end, and a C-Flash based, rewritable, non-volatile memory module to achieve full on-chip system integration. The complete system was designed and fabricated in the TowerJazz 0.18 μm CMOS technology without any additional mask adders. By embedding the RF, memory, and digital components together upon a single substrate in a standard digital process, the low-cost aspirations of the “5-cent RFID tag” become feasible. Design considerations, analysis, circuit implementations, and measurement results are presented. The entire system was fabricated on a 3.6 mm × 1.6 mm (6.9 mm2) die with the integrated antennas comprising 82% of the silicon area. The total read power was measured to be 13.2 μW, which is sufficiently supplied by the on-chip energy harvesting unit.

W-Band CMOS on-chip energy harvester and rectenna

This paper presents the first fully on-chip integrated energy harvester and rectenna at the W-Band in 65nm CMOS technology. The designs are based on a 1-stage Dickson voltage multiplier. The rectenna consists of an on-chip integrated dipole antenna with a reflector underneath the substrate to enhance the directivity and realized gain. The energy harvester and rectenna achieve a power conversion efficiency of 10% and 2% respectively at 94GHz. The stand-alone harvester occupies only 0.0945mm2 including pads, while the fully integrated rectenna occupies a minimal chip area of 0.48mm2.

A Wide-Band CMOS to Waveguide Transition at mm-Wave Frequencies With Wire-Bonds

In this paper a two-step transition between a CMOS chip and a WR-10 waveguide is investigated. The transition between a coplanar waveguide (CPW) on Duroid to W-band aluminum waveguide is studied and measured results show a bandwidth of 49% (67-110 GHz), an average insertion loss of 0.35 dB, and return loss below -10 dB throughout the entire band. Wire-bonding is then investigated as a connection between on-chip CMOS ground-signal-ground (GSG) pads to the Duroid CPW where the CMOS to printed circuit board transition measured results show an average 1-dB loss (including the CMOS GSG launcher) in the W-band. The full transition is also used to demonstrate packaging of a 100-GHz voltage-controlled oscillator in 90-nm CMOS where the RF signal was transmitted successfully with an average 2.5-dB loss (which includes a 2-cm Duroid CPW line) compared to on-chip probing measurement results.

A 67-110GHz CMOS to WR-10 waveguide transition using wirebonds and wideband microstrip launcher

In this paper a two-step transition between a CMOS chip and a WR-10 waveguide is designed and implemented. First, a CPW on Duroid to W-band aluminum waveguide is realized with a bandwidth of 49 % (67-110 GHz), an average insertion loss of -0.35 dB and reflection loss below -10 dB throughout the entire band. Then, wire-bonding the CMOS G-S-G pads to the Duroid CPW introduces an average 0.2 dB loss in the W-band. A 100 GHz RF signal of a 90nm CMOS VCO was transmitted successfully using this transition with less than 2 dB loss (which includes a 2-cm Duroid CPW line) compared to on chip probing measurement results.

A 0.3 THz Radiating Active

In this paper, a ×27 radiating active frequency multiplier chain at 288 GHz is presented. The circuit output is connected to a single on-chip ring antenna radiating a record high total radiated power of 1 mW for a DC power consumption of 284 mW at 288 GHz. The circuit has a -3 dB bandwidth of 15 GHz (277-292 GHz), an EIRP of +10.2 dBm and a record radiated DC-to-RF efficiency of 0.34% for a radiating frequency multiplying chain, enabled by direct drain transistor to on-chip antenna connection. The antenna has a measured directivity of +10.2 dBi at 288 GHz. Realized in a 65-nm technology, this is the first CMOS integrated locked radiating source to achieve 1 mW of radiated power above 0.2 THz.

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In this paper a packaged X-band to W-band x9 active multiplying chain in CMOS 65 nm technology is presented. The integrated circuit was packaged and connectorized to allow FMCW Radar system operation. Wire bonds and a microstrip-to-waveguide transition were used at the output. On-chip probing showed a maximum output power of +9.7 dBm, a 3 dB bandwidth of 13% (86-98 GHz) while consuming 280 mW of DC power. An EIRP of +29.8 dBm was measured at 92 GHz by connecting a WR-10 pyramidal horn antenna to the WR-10 package output. The generic package can be employed to any circuit with an output signal from 67 to 110 GHz introducing an average 3.5 dB insertion loss in the package RF path.

Frequency Multiplier Chain With 1 mW Radiated Power in CMOS 65-nm

A non-coherent amplitude shift keying (ASK) W-band packaged transceiver in 65 nm CMOS technology is presented. The transceiver architecture is based on an innovative bi-directional topology with a maximum data rate of 10 Gbps limited by the measurement equipment. An output power of -2.3 dBm at 107 GHz and 10 Gbps modulated signal is measured on-chip in the transmit mode. In the receive mode a BER<;10-12 was achieved with data rates up to 8.5Gbps. The packaged transceiver demonstrates 10Gbps wireline and wireless bi-directional half-duplex communication with only 34 mW of DC power consumption. The design occupies only 0.35 mm2 including pads.

A packaged 86–98 GHz CMOS transmitter for FMCW radar applications with 30 dBm of EIRP

A novel concept is introduced for generating high power frequency locked THz radiating based on CMOS chips. The concept is based on an array of CMOS VCO chips with on-chip ring antennas. With fundamental mm-wave oscillation around 115 GHz, the 3rd harmonic of 0.35 THz is radiated with record total radiated power (TRP) of -4.3 dBm, EIRP of +3.8 dBm, DC-to-THz efficiency of 1.4% and phase noise better than -95 dBc/Hz at 10 MHz offset. Using a buffer-less Colpitts topology both improves the output power and efficiency but also allows wireless locking of the VCO fundamental frequency using the on-chip antenna, which is an RF-choke for that frequency. This allows wireless coupling between array CMOS chip elements integrated on-board for mutual locking and also wireless locking to an external D-band reference. The concept is demonstrated using a 1×4 array of CMOS radiating chips. The sources can be tuned from 343 to 347 GHz and the injection locking range is around 80 MHz. The 1×4 array has an EIRP of +13.8 dBm, a TRP and DC-to-THz efficiency of +1 dBm and 1.2%, respectively. The 1×4 array locked signal follows the phase noise of the external reference (+9.5 dB) up to a locking range around 80 MHz. This new concept enables simple and cost effective locked CMOS THz scalable source arrays.