Elio Guidetti

pH sensing properties of graphene solution-gated field-effect transistors

The use of graphene grown by chemical vapor deposition to fabricate solution-gated field-effect transistors (SGFET) on different substrates is reported. SGFETs were fabricated using graphene transferred on poly(ethylene 2,6-naphthalenedicarboxylate) substrate in order to study the influence of using a flexible substrate for pH sensing. Furthermore, in order to understand the influence of fabrication-related residues on top of the graphene surface, a fabrication method was developed for graphene-on-SiO2 SGFETs that enables to keep a graphene surface completely clean of any residues at the end of the fabrication. We were then able to demonstrate that the electrical response of the SGFET devices to pH does not depend either on the specific substrate on which graphene is transferred or on the existence of a moderate amount of fabrication-related residues on top of the graphene surface. These considerations simplify and ease the design and fabrication of graphene pH sensors, paving the way for developing low c...

A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chip

We describe a voltage-scalable 32b microprocessor system-on-chip (SoC) that provides both moderate peak performance (up to 82.5 MHz at 1.2 V) and extreme energy efficiency (10.2 pJ/cycle at 0.54 V) for applications with limited energy budgets and time varying processing loads. The SoC employs low-voltage 8T SRAMs operating down to an array voltage of 0.4 V. Memory access energy is further reduced by miniature (128 B) latch-based instruction and data caches. On chip clock generation and the ability to boot from a small external serial flash ROM makes for a very small overall system.

Implementing a 1GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology

This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and memory hierarchy techniques help Godson-2E to achieve high performance. The Godson-2E processor has been physically designed in a 7-metal 90nm CMOS process using the cell-based methodology with some bit-sliced manual placement and a number of crafted cells and macros. The processor can be run at 1GHz and achieves a SPEC CPU2000 rate higher than 500.

14.1 A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems

A booming number of computer vision, speech recognition, and signal processing applications, are increasingly benefiting from the use of deep convolutional neural networks (DCNN) stemming from the seminal work of Y. LeCun et al. [1] and others that led to winning the 2012 ImageNet Large Scale Visual Recognition Challenge with AlexNet [2], a DCNN significantly outperforming classical approaches for the first time. In order to deploy these technologies in mobile and wearable devices, hardware acceleration plays a critical role for real-time operation with very limited power consumption and with embedded memory overcoming the limitations of fully programmable solutions.

The Orlando Project: A 28 nm FD-SOI Low Memory Embedded Neural Network ASIC

The recent success of neural networks in various computer vision tasks open the possibility to add visual intelligence to mobile and wearable devices; however, the stringent power requirements are unsuitable for networks run on embedded CPUs or GPUs. To address such challenges, STMicroelectronics developed the Orlando Project, a new and low power architecture for convolutional neural network acceleration suited for wearable devices. An important contribution to the energy usage is the storage and access to the neural network parameters. In this paper, we show that with adequate model compression schemes based on weight quantization and pruning, a whole AlexNet network can fit in the local memory of an embedded processor, thus avoiding additional system complexity and energy usage, with no or low impact on the accuracy of the network. Moreover, the compression methods work well across different tasks, e.g. image classification and object detection.

An Ultra-Low Power Data Aggregation System for Wireless Micro Sensor Networks

The paper introduced a novel methodology, for reducing energetic consumption, during data compression in homogenous sensor nodes organized in a cluster based network. Our approach employed a bit-wise operator previously used in the context of the reduction of dynamic energy in external buses. The document defined the compression and decompression laws based on this operator, in a conceptual way much similar to the code division multiple access (CDMA) systems, used in the telecommunication scenario. Each sensor has internally associated a digital signature, used in the compression stage. The host computer tries to recover the original waveform executing the cited operator and applying the inverse signature. The original data has been corrupted by an interference process, which depends on the presence of the other users in the same cluster. The host computer is able to select the best signatures, mostly reducing the energy of the interfering process. Simulations conducted with Matlab and SimplePower indicated our approach gains an 85% in energy consumption compared to the simpler algorithm up to now known (Least Mean Squares). Moreover, simulations verified the host has the capability to recover the transmitted waveforms in their fundamental harmonic members.