Nitin Chawla

A 360mW 105Mb/s DVB-S2 Compliant Codec based on 64800b LDPC and BCH Codes enabling Satellite-Transmission Portable Devices

The design of a full broadcast + interactive services compliant 2nd generation satellite digital video broadcast (DVB-S2) codec is presented.

14.1 A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems

A booming number of computer vision, speech recognition, and signal processing applications, are increasingly benefiting from the use of deep convolutional neural networks (DCNN) stemming from the seminal work of Y. LeCun et al. [1] and others that led to winning the 2012 ImageNet Large Scale Visual Recognition Challenge with AlexNet [2], a DCNN significantly outperforming classical approaches for the first time. In order to deploy these technologies in mobile and wearable devices, hardware acceleration plays a critical role for real-time operation with very limited power consumption and with embedded memory overcoming the limitations of fully programmable solutions.

A 1 GHz Digital Channel Multiplexer for Satellite Outdoor Unit

A digital channel multiplexer for satellite outdoor unit running at 1 GHz clock frequency is implemented in 65 nm CMOS mixed oxide dual voltage technology. This multiplexer, based on a 1 GS/s digital signal processor (DSP) approach with 500 MHz input and output bandwidth, embeds two 8 bit 1 GS/s analog-digital converters (ADCs) and two 8 bit 1 GS/s digital-analog converter (DACs). It consumes less that 1022 mW at ambient temperature while achieving noise rejection up to 42.5 dB on a single tone, and > 37 dB on modulated satellite channels.

A 1GHz digital channel multiplexer for satellite OutDoor Unit based on a 65nm CMOS transceiver

Satellite digital TV broadcast reception today requires a multiple Low-Noise Block (multi-LNB) head on the dish, as well as a multi-tuner set-top box (STB). Connecting multiple OutDoor Units (ODU) to the set-top boxes traditionally needed multiple cables. A first step has been achieved with so-called satellite Channel Stacking Switch™ technology (CSS), able to deliver the full suite of TV programs to all STBs in a single home through a reduced number of cables. However, this pure analog/RF technology does not offer enough flexibility in terms of the number of simultaneous users (12 users maximum) and requires multiple external components like SAW filters, increasing significantly the cost of the solution [1]. Introducing digital processing in this RF dominated application to sort and assemble user channels removes the need of in-band SAW filters, offers full flexibility of channel selection, and supports up to 50 users simultaneously.

The Orlando Project: A 28 nm FD-SOI Low Memory Embedded Neural Network ASIC

The recent success of neural networks in various computer vision tasks open the possibility to add visual intelligence to mobile and wearable devices; however, the stringent power requirements are unsuitable for networks run on embedded CPUs or GPUs. To address such challenges, STMicroelectronics developed the Orlando Project, a new and low power architecture for convolutional neural network acceleration suited for wearable devices. An important contribution to the energy usage is the storage and access to the neural network parameters. In this paper, we show that with adequate model compression schemes based on weight quantization and pruning, a whole AlexNet network can fit in the local memory of an embedded processor, thus avoiding additional system complexity and energy usage, with no or low impact on the accuracy of the network. Moreover, the compression methods work well across different tasks, e.g. image classification and object detection.