Elke Zakel

Fine pitch stencil printing of Sn/Pb and lead free solders for flip chip technology

This paper presents a flip chip technology based on an electroless Ni/Au bumping process which has been developed by IZM/TUB. Nickel bumps offer a surface with very good suitability for flip chip soldering. In the following an interconnection method is described which uses ultra fine pitch stencil printing of solder paste on wafers, ceramic and organic substrates. The eutectic Pb/Sn solder alloy is by far the most commonly used solder in industry. Facing the ecological challenge and federal legislation the paste suppliers are developing lead free solder pastes. Due to the fact that the variety of solder pastes is still growing it is necessary to find an ideal alloy for a specific application. Therefore, in comparison to eutectic Sn/Pb solder different alloys, e.g. Bi/Sn, Sn/Bi/Cu, Sn/Ag, Sn/Cu, Au/Sn are investigated in this paper. In the first part of this paper a low cost flip chip technology based on chemical Ni/Au bumping and solder printing is presented. For this the basic process steps and key aspects are described in detail. The experimental results of an ultra fine pitch technique on wafers and on substrates are shown as well. The second part of this paper presents a comparison of the properties of different solder pastes concerning the usability for flip chip technology. For this, flip chip soldering using dies with Ni/Au bumps was performed on ceramic and FR-4 substrates. The quality of the flip chip joints were investigated by metallurgical cross sections and electrical and mechanical measurements. Finally, the reliability results of these joints after thermal cycling are presented. A comparison of underfilled and nonunderfilled flip chip devices will complete the investigations.

Flip chip attachment using anisotropic conductive adhesives and electroless nickel bumps

Flip chip attachments provide the highest interconnection density possible, which makes this technology very attractive for use with liquid crystal display (LCD) packaging methods. This technology stimulated the development of new interconnection techniques, such as anisotropic adhesives. However, several factors have hindered the wide use of this technology. These factors include the availability and costs of bumped wafers. IZM and TU-Berlin have addressed both of these concerns by establishing a wafer-bumping facility which uses electroless nickel bumps. The combination of anisotropic adhesives and electroless nickel bumps has the potential for a low-cost chip on glass (COG) and chip on flex (COF) bonding technology. In this paper, two types of anisotropic adhesives were studied with an emphasis on the properties of COG and COF interconnections. The electrical and mechanical performance of the adhesive bonds was studied by evaluating initial contact resistance and mechanical adhesion as a function of temperature and humidity.

Electroless deposition of bumps for TAB technology

Electroless nickel plating was investigated for bumping. Electroless nickel bumps with a height of 265 mu m have been selectively formed on aluminium bondpads. The nickel bumps have been inner-lead-bonded by gang bonding to a tape with a thick layer of tin. The adhesion of the bumps was investigated as a function of the pretreatment of the bondpads. It is noted that electroless bumping offers the greatest advantage of reducing the costs of the bumping process because no sputtering equipment or lithography is required. This can be very important if only small quantities of bumped dies are required because the process is independent of substrate size. Electroless bumping may become an alternative to conventional wafer bumping by electrodeposition at least for certain applications.<<ETX>>

Wafer level CSP using low cost electroless redistribution layer

A driving force to achieve increased speed and performance along with higher I/O count is the Flip Chip (FC) Technology which has therefore an high level of importance for a variety of applications. A breakthrough, however, will be the use of flip chip due to cost reduction. For this aim it is essential to use low cost bumping techniques. However, to provide FC technologies also for devices with high I/O count and high pin density applications like Microcontrollers, RAMBUS devices, etc.... it is necessary to redistribute the historically peripheral bond pads with ultra fine pad pitch into a wafer level CSP. This paper describes a low cost electroless Ni/Au Under Bump Metallization (UBM) and a wafer level redistribution process based on electroless copper circuitization. It includes the use of a novel plasma enhanced chemical vapour deposition (PECVD) process to deposit a bifunctional nanolayer acting as an adhesion promotor and as a catalyst for electroless copper deposition. The described techniques are suitable for all wafer passivation types, which are used in industry today. The complete redistribution process is based on batch processing and less masking and photoimaging steps. By using the electroless Nickel process and wafer level stencil solder printing the process is highly cost efficient and has large volume manufacturing capability. Results and also reliability measurements will be presented. Finally a roadmap regarding the implementation of this process into backend high volume production is shown.

Mounting of high power laser diodes on diamond heatsinks

This work describes the mounting of commercial 1 W laser diodes soldered on chemical vapor deposition (CVD) diamond heatsinks using Au(80)Sn(20)-solder. With a standard heatsink metallization, the laser diode suffers under high stress. This can be seen in the power-current characteristic and the spectrum as well as in the near and farfield beam pattern, With a modification of the heatsink metallization layer, it was possible to obtain a reproducible mounting process. We compare the electrical and optical characterization of the typical standard heatsink metallization with the modified metallization. So we are able to qualify the mechanical stress in the laser diode. For a better understanding of the modified metallization SEM and EDX analyses are performed. For the quantification of the stress an analytical model is used to compute the maximal shear, tensile, and peel stress. Furthermore, the quality of the bond interface is investigated with high resolution X-ray microscopy. No voids are found. Additionally, the results of a standard burn-in and the first accelerated aging tests to prove the reliability are presented.

Au-Sn bonding metallurgy of TAB contacts and its influence on the Kirkendall effect in the ternary Cu-Au-Sn system

The authors summarize work done on different Au-Sn-Cu and Au-Cu metallurgies in the inner lead bond (ILB) area. The influence of Kirkendall-pore formation in the Cu-Au-Sn system as a degradation mechanism is shown. This effect together with the formation of a new type of ternary intermetallic compound is observed during thermal aging in contacts with a direct interface between the eutectic 80/20 Au-Sn alloy and copper. The zeta-phase (Au/Sn 90/10) acts like a diffusion barrier, which inhibits the pore formation associated with copper diffusion. The composition of the ternary intermetallic compounds, their growth constant, and their activation energy were determined. The possibility of increasing the contact reliability by producing a reliable Au-Sn metallurgy during the ILB-process is shown. >

Reliability investigations of fluxless flip-chip interconnections on green tape ceramic substrates

The use of flip chip bonding technology is having a growing importance in the construction of novel hybrid microelectronic devices and is of increasing interest for the application in consumer oriented products. Especially fluxless processes are demanded for the compatibility with underfill materials and for an improved reliability performance. This paper describes the development of a fluxless flip chip mounting process by use of Au/Sn solder bumps on different thick film metallizations of green tape ceramic substrates. The results of the investigations show, that fluxless flip chip bonding is possible directly on Au as well as Ag and Pd/Ag thick film pattern and via metallizations. The flip chip assembly process is performed by single chip bonding and requires substrates with narrow planarity tolerances. For the different substrate metallizations the range of optimal bonding parameters are determined. Best mechanical and electrical results are achieved with Au/Sn bumps on Pd/Ag thick film metallizations. For this system the investigations are performed, to show the influence of the chip size and bump height on reliability. The fatigue life of solder joints, which is limited by the thermal expansion mismatch between chip and substrate could be significantly increased by an adequate encapsulation process. The reliability results of the fluxless flip chip joints after thermal cycling, temperature storage, temperature-humidity and pressure cooker tests are presented.

A roadmap to low cost flip chip and CSP using electroless Ni/Au

Flip chip (FC) technology is gaining an increased level of importance for a variety of applications based on flip chip on board or flip chip in package. The first driving force for the introduction of this technology was the need to achieve increased speed and performance along with higher I/O count. A breakthrough, however, will be the use of flip chip due to cost reduction. For this aim, it is essential to use low cost bumping techniques in combination with an SMT-compatible assembly method. The FC techniques presented in this paper are all based on an electroless Ni/Au bumping process which has been developed by TUB/IZM and implemented into production by Pac Tech. This paper shows a roadmap based on electroless nickel/gold bumping for all flip chip interconnection technologies currently used in industry. Also, the roadmap to future developments in the semiconductor industry based on 300 mm wafers and the use of new pad metallisations such as Cu is shown. The compatibility of electroless nickel bumping in particular with these new technologies to be implemented in wafer manufacturing in the next millenium shows that this key technology offers a roadmap to flip chip technology not only for products and wafer technologies in use at present but for next generation wafer technologies. This paper looks at electroless Ni as a basis for anisotropic conductive adhesive (ACF) flip chip assembly, for polymeric flip chip assembly (conductive adhesive) and for soldering and direct chip attach-type applications using different solder alloys.

Fluxless die bonding of high power laser bars using the AuSn-metallurgy

This paper presents a new concept for a fluxless package design for commercial high power laser bars. The laser bars are soldered on CuW heatsinks using Au(80)Sn(20) solder. Then a Cu lead is bonded with the FPC method (Fiber-Push-Connection) as a cap and electrical contact. Finally, the heatsink is mounted on a Cu microchannel cooler with Pb(37)Sn(63). We describe the mounting processes in detail, showing the large bonding window for soldering with Au(80)Sn(20), which is necessary for industrial production. The metallurgy of the Au(80)Sn(20) bonding interface is not dependent on the bond parameters in the area of the bonding window. Electro-optical characterizations show excellent performance of the laser bars. An accelerated aging test gives a first indicator of the high reliability of this package concept.

Fluxless flip chip assembly on rigid and flexible polymer substrates using the Au-Sn metallurgy

The application of the Au-Sn system for flip chip assembly offers the advantage of a fluxless soldering process. This can be attributed to the excellent wetting properties of Au-Sn and Sn alloys on Au-surfaces. Depending on the chosen Au-Sn or Au-Sn/Pb alloy composition, soldering in a wide range of temperatures between 200 to 380/spl deg/C is possible. For flip chip interconnections, two approaches are presented. One consists in the application of electroplated eutectic Au/Sn 80/20 solder bumps on substrates with Au or Ni/Au as final metallizations. The second approach uses gold bumps on substrates with Sn or eutectic SnPb solder as final metallization. In this case, the Au-Sn alloy is formed during the flip chip soldering process. This solution permits soldering of the flexible and low cost Au- stud bumps produced using thermosonic wire bond equipment. The bond parameters, the material requirements and limitations of the polymer substrates consisting of rigid and flexible printed wiring boards are discussed. A metallurgical study of the formed Au-Sn alloys and intermetallic compounds and their influence on the reliability of the FC-assembly is presented.<<ETX>>