H. Oppermann

Assembly and reliability of flip chip solder joints using miniaturized Au/Sn bumps

Flip chip assembly experiments using small electroplated Au/Sn bumps, i.e. bumps of 50 /spl mu/m in diameter and less, are carried out. After plating the bumps consist of a Au layer with a thinner Sn layer on top. Normally a reflow process in which the bumps are heated up to more than 280/spl deg/C follows after which the bumps consist of a thick Au layer with an eutectic solder cap on top and a /spl zeta/-phase layer in between. However, the experiments prove that due to geometrical reasons as plated bumps rather than reflowed ones shall be used for bump sizes below 50 /spl mu/m in diameter in order to achieve a high yield flip chip assembly process. Furthermore thermal cycling tests were carried out using flip chip assemblies consisting of a GaAs die soldered to a BCB thin film Silicon substrate. Assemblies with Au/Sn bumps of the size of 30 /spl mu/m and 50 /spl mu/m in diameter were tested this way.

Biocompatible hybrid flip chip microsystem integration for next generation wireless neural interfaces

Chronically implantable, wireless neural interfaces require biocompatible, long term stable, and high density integration of all functional sub-components. For this, the integration and interconnection concept of the wireless neural interface was proposed and interconnection materials and methods were investigated and characterized. The module consists of an electronics IC assembled to an electrode array. Thin film flex coils are glued onto the back side of the IC. The IC was interconnected by AuSn reflow flip chip bonding on the backside of the Utah electrode array (UEA) and off-chip electric components were SnCu0.7 soldered on the integrated IC/UEA module to guarantee a reliable connectivity

Precise flip chip assembly using electroplated AuSn20 and SnAg3.5 solder

In order to reduce costs in packaging especially for optoelectronic devices technologies are desirable that enable precise assembly at low cost. A flip chip assembly approach is presented using the self-alignment mechanism in combination with mechanical stops. Besides eutectic AuSn20 solder (80 wt.-% Au, Tm = 280 degC) which is widely used in optoelectronics the eutectic SnAg3.5 solder (96.5wt.-% Sn, Tm = 221 degC) was tested as an alternative which is compatible to organic substrates. Both types of solder bumps were deposited using electroplating and were reflowed prior to flip chip assembly. The phase transformations taking place during the reflow of Au/Sn solder bumps are described. Furthermore, flip chip reflow soldering experiments of test vehicles using AuSn20 and SnAg3.5 solder proved that it is possible to achieve self-alignment in three directions. The final position of the chips in regard to the substrates was solely determined by the mechanical stops on both chip and substrate side being in direct contact to each other

Fluxless flip-chip attachment techniques using the Au/Sn metallurgy

With the use of the Au/Sn system as solder metallurgy different fluxless flip-chip processes are possible. In the studies for this paper Au/Sn bumped chips are used for soldering in an infrared oven under activated atmosphere with the self-alignment mechanism. A new approach is the successful application of the Au/Sn metallurgy for vapor phase soldering which provides the self-alignment effect as well. Flip-chip bonding on rigid and flexible substrates using a pulse heated thermode is also demonstrated. The scope of this paper is to show the development of different fluxless flip-chip processes with Au/Sn metallurgy on thin film and thick film substrates. The wetting of the pads, the fillet formation and the growth of /spl zeta/-phase are the major subjects of the studies as they determine the bonding result. Shear tests were performed in order to quantify the quality of the interconnection. The results obtained by the different methods are compared and conclusions about the investigated processes drawn.

Technology Requirements for Chip-On-Chip Packaging Solutions

The trend towards smaller, lighter and thinner products requires a steady miniaturization which has brought-up the concept of Chip Scale Packaging (CSP). The next step to reduce packaging cost was the chip packaging directly on the wafer. Wafer Level Packaging (WLP) enables the FC assembly on PWB without interposers. New and improved microelectronic systems require significant more complex devices which could limit the performance due to the wiring of the subsystems on the board. 3-D packaging using the existing WLP infrastructure is one of the most promising approaches. Stacking of chips for chip-on-chip packages can be done by wafer-to-wafer stacking or by chip-to-wafer stacking which is preferable for yield and die size considerations. This chip-on-chip packaging requires a base die with redistribution traces to match the I/O layout of both dice. This allows the combination of the performance advantage of flip chip with the options of WLP. To avoid the flip chip bonding process the thin chip integration (TCI) concept can be used. Key elements of this approach are extremely thin ICs (down to 20 μm thickness) which are incorporated into the redistribution. This technology offers excellent electrical properties of the whole microelectronic system. The focus of this paper will be the technology requirements for the realization of different kinds of chip-onchip packages.

Behaviour of platinum as UBM in flip chip solder joints

The use of flip chip technology requires necessarily the implementation of bumps either on the chip pads or on the corresponding pads on the substrate side or both. These bumps provide the electrical as well as the mechanical interconnection. Applying solder bumps for flip chip interconnection it is necessary to have a solderable under bump metallization (UBM) which at the same time provides a diffusion barrier. This investigation is focused on the behaviour of Platinum as UBM or part of it and points out the advantages and disadvantages of this metal in combination with a flip chip solder bump on top of it. Platinum was thereby either evaporated and covered with a goldflash or directly mechanically bumped on the Aluminum pad metallization. The evaporation is based on wafer level processes and can therefore be used for high volume production. Because of the very flexible procedure the mechanical stud bumping is suitable for single chips, substrates, and wafers. The Platinum stud bump was leveled after bumping to have a smooth UBM surface for solder application. For solder bumping in both cases mechanical bumping of solder balls or studs with PbSn and PbSnAg was used. After high temperature storage at 100, 125, 130, and 150/spl deg/C the phase formation of Pt-Sn intermetallics was investigated. The adhesion of the solder bumps was evaluated by sheartesting with respect to the detected shear mode. To characterize the solder interconnections cross-sectioning was performed and the growing of Pt-Sn phases was analyzed by SEM and EDX. Especially for the evaporated UBM the phase formation is of great interest because of the consumption of the Pt layer, which directly influences the reliability of the flip chip interconnection.

Reliability investigations for flip-chip on flex using different solder materials

Flip chip assembly on flexible organic substrates is facing increasing interest. In consumer products such as mobile phones or pagers, the assembly of the drivers of the LCD displays can be realized this way. Also there is a growing demand for Chip Size Packages (CSP). As a low cost version, CSPs based on flexible interposers have been developed. Especially for this application the reliability of the assemblies is important. Little is known about the aging behavior of these packages with different solder materials such as Pb-Sn and Au-Sn on standard tape metallizations as Cu-Au or Cu-Ni-Au. The impact of the bumping technology on the reliability is also a subject. Electroplated bumps are studied in comparison with meniscus bumps. Based on electroless Ni bumping, this cost effective technology is especially suited for flip chip on flex as the solder volume deposited is very small. In order to make useful predictions about the reliability of a metallurgical system it is necessary to understand the basic reactions involved. The scope of the investigations presented in this paper is to gain the data on interdiffusion in these systems, on the formation and growth of intermetallic phases. The impact of the presence of intermetallics and voids on the mechanical reliability is determined. The test program includes annealing of the flip chip assemblies at different temperatures and thermal cycling. Electrical measurements (Daisy chain) and shear tests are performed to determine the electrical and mechanical degradation of the solder joints.

Reliability of electroless nickel for high temperature applications [flip chip packaging]

Electroless Ni/Au plating is interesting for flip chip due to its bumping cost reduction potential. Electroless Ni bumping provides selective autocatalytic deposition on Al wafer pads. For flip chip soldering, selective solder deposition on Ni bumps is essential. The greatest cost reduction potential is in solder paste stencil printing. The Ni under-bump metallization (UBM)/PbSn eutectic solder system shows excellent reliability. Results of long-term aging at 150/spl deg/C and reliability tests are presented. AuSn or PbSn eutectic solders are used for high temperature applications. For 150/spl deg/C-250/spl deg/C operation, extended Ni-UBM reliability requirements are given. Electroless Ni bumps show an amorphous structure. At high temperatures, relaxation and crystallization effects were noted. During relaxation (>230/spl deg/C), atoms move over small interatomic distances to a new reduced volume arrangement. Amorphous structure change could not be observed for this effect. At temperatures >320/spl deg/C, crystallization with Ni and Ni/sub 3/P formation occurs. Crystallization includes further NiP alloy volume reduction, which can lead to Si cratering below Ni if an improper UBM thickness is used. Ni bump geometries are discussed. To study the electroless Ni structure, thermal analysis (DSC, thermomechanical analysis), X-ray diffraction and other measurements were carried out. Simplified Si crack formation models due to structure transformation are shown. Results of Ni-UBM phase formation and growth with AuSn/PbSn solders at 200/spl deg/C are given. The influence of P on phase growth and impact on reliability at high temperatures are discussed.

Thin film substrate technology and FC interconnection for very high frequency applications

High speed interconnections for the next generation Internet or high frequency measurement systems need ultra fast photodetectors and appropriate high frequency transmission lines. A highly critical aspect for packaging these devices is the interconnection and the appropriate substrate technology. Thin film substrates using BCB are a suitable approach due to the high accurate manufacturing technology and the possibility to use low k dielectrics. FC assembly is the best interconnection technology for this very high frequency application, and it is already proven in production. Ultra-fast InP-photodetectors (100 GHz) with CPW signal pads (GSG) had to be connected to a 1 mm RF plug via a micro-stripline (MS). Flip chip bumps on InP and interconnection schemes for CPW to MS transitions were investigated. The electrical performance of these structures has been simulated and is discussed with respect to the electrical tests done on the samples. The process compatibility of the chosen materials was verified separately and the properties adapted, if necessary. Reliability tests have been performed on test samples and are discussed also in the paper with respect to substrate technology and to the FC assembly

Reliability investigations of flip-chip solder bumps on palladium

The choice of the solder joint metallurgy is a key issue especially for the reliability of flip chip assemblies. Besides the systems which are already widely used and well understood, new materials are emerging as solderable under bump metallizations (UBMs). Palladium can be used as a basis for flip chip bumps in different ways: For single chip bumping Pd stud bumps form a solid core under the solder layer. These hard core solder bumps are an adequate solution if the dies are not available on wafer level and the chosen assembly technology is flip chip soldering. On wafer level electroless deposition of Palladium bumps is available on which solder can be deposited e.g. by stencil printing or meniscus bumping. The scope of this paper is to summarize the results from aging of eutectic Pb/Sn solder on Palladium stud bumps. The intermetallic growth which is observed and its impact on the mechanical and electrical reliability are investigated. Based on this data Palladium as an under bump metallization can be compared to alternative materials such as Nickel.