Eman El Mandouh

Automatic generation of hardware design properties from simulation traces

This paper studies the problem of automatic assertion extraction from simulation traces. Previous approaches to the assertion generation problem have focused on a single aspect of automatic assertion extractions, and have yielded often unfavorable results. We propose a framework that combines searching for known assertion via templates with frequent and sequential patterns mining, while constraining the search by some knowledge about the design. These constraints can be automatically extracted using static analysis methods from the Register Transfer Level (RTL) description of the design, or as a user input to the assertion detector. Our experimental results show that this approach helps in the detection of assertion patterns that are typically common and widely used in todays RTL designs.

Estimation of formal verification cost using regression machine learning

Formal Verification is a computationally expensive step in the verification of todays complex hardware designs. Effective results can be obtained from formal runs by planning ahead the effort and cost that are required for them. Additionally estimating in-advance the expected formals complexity promotes a lot of potential tricks and clever setup techniques to overcome the initial push-button capacity limitation of the formal verifies and improve their capabilities to handle designs with higher complexity. This paper illustrates the application of regression machine learning (ML) techniques to build an estimation model for the cost of formal verification. Up to 10,000 formal verification runs on RTL designs with good varieties of design/properties attributes are used to learn the relationship between HW designs and the final formal cost in terms of formal run time. We demonstrate the use of Ridge-Regression to decide on the bias-variance trade-off during the regression-model design step as well as the application of Lasso-Regression for the feature selection phase. Finally a comparison between the proposed multiple linear regression approach and another non-parametric K-nearest neighbors kernel based regression technique is done to conclude on the presented work. Our results indicate how the proposed model managed to estimate with reasonable error ratio the expected formal verification effort for new-to-verify HW designs.

Application of Machine Learning Techniques in Post-Silicon Debugging and Bug Localization

As the size of hardware (HW) design increases significantly, a huge amount of data is generated during the design simulation, emulation or prototyping. Debugging large HW designs becomes a tedious, time consuming and a bottleneck task within the function verification activities. This paper proposes the utilization of machine learning techniques to automate the diagnosis of design trace dump as well as helping in bug localization during post-silicon validation. Our framework starts by signal selection algorithm that identifies which signals to monitor during design execution. Signal selection depends on signal types as well as their connectivity network. The design is then executed and the trace dump is saved for offline analysis. Big-Data processing technique, namely, Map-Reduce is used to overcome the challenge of processing huge trace dump resulted from design running on FPGA prototype. K-means Clustering method is applied to group trace segments that are very similar and to identify the ones with a rare occurrence during the design execution. Additionally, we propose a bug localization framework in which X-means clustering is used to group the passing regression tests in clusters such that buggy tests can be detected when they fail to be assigned to any of the trained clusters. Our experimental results demonstrate the feasibility of the proposed approach in guiding the debugging effort using a group of industrial HW designs and its ability to detect multiple design injected defects using mutation-based-testing method.

Automatic generation of functional coverage models

This paper proposes a framework to automatically generate functional coverage model for the Design under Verification (DUV). The coverage goals are identified to cover different combinations of the design inputs, outputs, Finite State Machines (FSMs) valid states/transitions and internal signals that control the guard expressions of the design control flow. Additionally the cross coverage of highly correlated design variables is added to the final coverage model and generated using data mining techniques. The proposed framework illustrates how formal methods can be used to automate the identification of unreachable coverage-points and then automatically generate the exclusion of those coverage items for final accurate coverage results calculations. Formal verification is also utilized to generate test scenarios (counter examples) for reachable coverage goals that have not been covered in initial random simulation runs. Our experimental results demonstrate the effectiveness of the proposed approach in closing the coverage loop for a set of todays RTL designs.

Tutorial 2: “Challenges of FPGA-based prototyping & debugging”

Software has come to dominate system-on-chip (SoC) development. It is increasingly common for the software effort to be on the critical path of the project schedule. Only FPGA-based prototyping provides both the speed and accuracy necessary to develop and validate complex software integration prior to silicon. The exciting benefits of an FPGA-based prototype are: • Quick fine tuning of hardware/software integration and software validation pre-silicon • In-system device validation with real-time interfaces and in end application • Extended register transfer level (RTL) testing and debugging

Accelerating the debugging of FV traces using K-means clustering techniques

As the size and the complexity of todays HW designs increase significantly, the debugging process becomes a real bottleneck in the function verification life cycle. A huge amount of debugging data is generated during HW design simulation, emulation and prototyping sessions. So any attempt to automate the diagnosis of the resulted data can be of great help to reduce the debugging time and increase the diagnosis accuracy. This paper proposes the utilization of machine learning techniques to automate the diagnosis of design trace history. k-means clustering technique is used to group the trace segments that own huge similarity and identify the ones that occur rarely during the design execution time. We demonstrate the application of the proposed framework in guiding the functional verification debugging effort using a group of industrial HW designs.

Guiding intelligent testbench automation using data mining and formal methods

Achieving coverage closure is consistently identified as one of the most difficult challenges during the functional verification of todays HW designs. Constraint random testing as well as coverage directed test generation (CDTG) techniques have been proposed previously with different degree of success. This paper presents a framework for speeding up the coverage closure of the design under verifications (DUV) using state of the art verification techniques. The framework starts with random simulation of the DUV followed by frequent pattern mining of simulation data to extract some valid design constraints. Simulation coverage database is analyzed and the coverage holes are identified and directed to the formal verification step, formal analysis is used to prove the unreachability of some coverage holes during simulation run. Formally proven unreachable cover items as well as automatically extracted design constraints are then fed as test template specification to direct the intelligent testbench generation to rapidly achieve the coverage of previously uncovered corner cases. Our experimental results demonstrate the effectiveness of the proposed approach in closing the coverage loop for a set of todays RTL designs.

Application of six-sigma DMAIC methodology in the evaluation of test effectiveness: A case study for EDA tools

As the scale and complexity of electronic designs increase, Electronic Design Automation (EDA) tools become much more sophisticated and have to face incredible challenges to keep peace with increasing technology and time-to-market pressures. EDA tools have to own a lot of quality attributes such as performance, scalability, usability as well as functionality. Testing of EDA tools is not about avoiding crashes or core dumps, but it is about verifying tools ability to work correctly on a wide range of input data, have higher capability to visualize and debug larger output dataset and to perform reasonably with less memory and time consumption [1]. The scope of testing in EDA tools is challenged by a constant increase in the tools code complexity and the expanding number of configurations, flows, combinations and platforms they should support. With shrinking product development life cycles and increasing time to market constraints, a robust quantitative method is needed to judge the pre-release testing effectiveness. This paper presents a case study for the application of six-sigma DMAIC(Define, Measure Analyze, Improve and Control) methodology to understand the main problems with some EDA tools testing process, to analytically reach solutions, to identify opportunities for improvement and to quantitatively monitor the effectiveness of the proposed solutions.

Tutorial 1: Foundations and Practical Design of CMOS Image Sensors

CMOS imagers are complex systems whose design requires quite different pieces of expertise, namely: pixels, analog signal processing, pixel readout and analog-to-digital conversion, digital signal processing, output drivers, etc. Confronting the design of new imagers require hence the concourse of multidisciplinary teams. However, because correct operation calls for the close interconnection among the different parts, global knowledge is mandatory for successful design. This is particularly pertinent for the newer generations of smart imagers required for high-end applications and/or requiring ultra-high image capture, on-chip image correction, scene interpretation, high dynamic range capture, etc. All these features demand architectural and circuital innovations and pose significant challenges to designers. Also, the increased interest on sensors capable of capturing 3-D scenes raise new challenges at circuit level related to the necessity to interface pixels different from those employed for 2-D capture, on the one hand, and to extract and convert to digital domain time information, on the other hand. This tutorial addresses the design of smart CMOS imagers by following a comprehensive and complete top-down approach where each subsystem is contemplated and described as a part of a whole. Starting the formulation of the performance metrics used to specify and characterize imagers, the tutorial explains how the subsystem behavior and non-idealities impact on the global imager metrics, thereby setting the basis to specify the subsystems for given global image sensor specs. Such methodology is illustrated in the tutorial via a dedicated, MATLAB-based modeling tool which will be employed to allow the attendees gaining insight on the impact of non-ideal sub-systems behaviors. The tutorial overviews the state-of-the-art regarding: pixels; analog signal processing and read-out circuitry; data conversion circuitry, covering both amplitude data converters (required for 2-D images) and time-to-digital converters (required for 3-D imagers); driving circuits. Practical design recipes are given for all these circuits. Architectures and circuit solutions employed for high dynamic range acquisition and embedded image processing are also reviewed. A case study is included where attendees are exposed to practical considerations to be taken during the design process, including the influence of packaging, optics and camera embedding.