Ashraf Salem

An efficient implementation of floating point multiplier

In this paper we describe an efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA. VHDL is used to implement a technology-independent pipelined design. The multiplier implementation handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a Multiply and Accumulate (MAC) unit. With latency of three clock cycles the design achieves 301 MFLOPs. The multiplier was verified against Xilinx floating point multiplier core.

Formal Semantics of Synchronous SystemC

In this article, a denotational definition of a synchronous subset of SystemC is proposed. The subset treated includes modules, processes, threads, wait statement, ports and signals. We propose a formal model for SystemC delta delay. Also, we give a complete semantic definition for the languages two-phase scheduler. The proposed semantic can constitute a base for validating the equivalence of synchronous HDL subsets.

Semi-formal verification of VHDL-AMS descriptions

In this paper a new technique for functional verification of VHDL-AMS descriptions is proposed. The technique is based on combining an equivalence checker, an analog simulator, and a term rewriting engine in a single tightly coupled verification environment. The proposed method verifies the equivalence between two VHDL-AMS architectures describing alternative implementations or different abstraction levels for the same A/MS design entity. The verification process is based on building comparator circuits for the analog outputs and miter circuits for the digital outputs. The miter circuit is verified using a novel SAT/BDD equivalence checking algorithm. The analog comparator circuit is verified using a set of rewriting rules. The equivalence of D/A & A/D converters is proved using a matching procedure.

A high performance algorithm for scheduling and hardware-software partitioning on MPSoCs

Multi-processor system-on-chip (MPSoC) is an integrated circuit containing multiple cores that implements most of the functionality of a complex electronic system and some other components like FPGA/ASIC on single chip. The most crucial things in such like these systems are the performance, energy, power and area optimization. Moreover, scheduling the tasks of an application on to the processors (cores) and HW/SW partitioning are inter-dependent in the traditional design space exploration process. In this paper, we propose an algorithm to produce the optimality of scheduling and optimize the number of cores that can be used and also reduce the overall execution time and number of buses on the chip by using efficient hardwaresoftware co-design partitioning technique. The viability and potential of the proposed algorithm is demonstrated by extensive experimental results to conclude that the proposed algorithm is an efficient scheme to obtain the optimality of scheduling and partitioning with hard and large task graph problems.

A novel feature set for deployment in ECG based biometrics

In the last two decades, the Electrocardiogram (ECG) was introduced as a powerful biometric tool for personal identification. The vast majority of publications in the ECG based biometrics domain have focused on extracting fiducial based features for use in the identification task. Fiducial based features refer to the landscape of an ECG, which encompasses three complex waves for each heartbeat. The fiducial based approach requires calculating amplitude and temporal distances between 11 fiducial points that represent the peaks, valleys, onsets and offsets of these waves. The purpose of this research is to investigate the efficiency of a subset of 23 fiducial features that has the advantage of relaxing the detection process to include only five points that represent the peaks and valleys of the three complexes. For comparison, a super set of 36 fiducial features and the subset of 23 features were examined using radial basis functions (RBF) neural network classifier. A dataset of 35 records of 13 subjects from PTB Physionet database was used for training and testing purposes. Thereafter, the generalization ability of the system to other datasets was tested using another set of 38 subjects from PTB database. The results show the ability of the proposed subset of 23 features to maintain the identification accuracy and provide better generalization results than the super set.

Denotational semantics of a synchronous VHDL subset

A denotational definition for a single clock synchronous subset of VHDL is proposed. The different domains for variables and signals, the elaboration of static environments, and the formulation of a simulation algorithm for the sub-language characterize this definition, and distinguish it from more traditional denotational semantics of programming languages.

Formal semantics of VHDL timing constructs

The aim of the work presented here is to enlarge the subset of VHDL which can be manipulated by formal verification tools by including the timing constructs. In this paper we give formal semantics for these constructs. And, we prove, partially, the equivalence between these semantics and the informal operational semantics of the language as defined in the VHDL language reference manual. Also, we show how these semantics can establish a basis for the construction of formal timing verifiers.

Real-Time Mobile Cloud Computing: A Case Study in Face Recognition

Face recognition has received attention from research communities recently. Law enforcement agencies are using facial recognition software as a crime-fighting tool. The quick increasing of Mobile Devices usage and the explosive growth of the mobile applications Mobile face recognition is one of important application. In the same time the mobile devices are facing many challenges in their resources as low computing power, battery life, limited bandwidth and storage. Mobile Cloud Computing (MCC) has been introduced to be a potential technology for mobile services and to solve the mobile resources problem by moving the processing and the storage of data out from mobile devices to the cloud. MCC offers abundant computing power that can be tapped easily. This paper gives explanation of MCC definition, Building private cloud with Open Source cloud OS, Face recognition as MCC Application with presenting the face detection and face recognition algorithms. Our results demonstrate that the proposed architecture is promising for real-time Mobile cloud computing by reducing the overall processing time.

A reconfigurable, pipelined, conflict directed jumping search SAT solver

Several approaches have been proposed to accelerate the NP-complete Boolean Satisfiability problem (SAT) using reconfigurable computing. In this paper, we present a five-stage pipelined SAT solver. SAT solving is broken into five stages: variable decision, variable effect fetch, clause evaluation, conflict detection, and conflict analysis. The solver performs a novel search algorithm combining state-of-the-art SAT solvers advanced techniques: non-chronological backjumping, dynamic backtracking and learning without explicit traversal of implication graph. SAT instance information is stored into FPGA block RAMs avoiding synthesizing overhead for each instance. The proposed solver achieves up to 70× speedup over other hardware SAT solvers with 200× less resource utilization.

A Shift Register based Clause Evaluator for Reconfigurable SAT Solver

Several approaches have been proposed to accelerate the NP-complete Boolean satisfiability problem (SAT) using reconfigurable computing. We present an FPGA based clause evaluator, where each clause is modeled as a shift register that is either right shifted, left shifted, or standstill according to whether the current assigned variable value satisfy, unsatisfy, or does not effect the clause, respectively. For a given problem instance, the effect of the value of each of its variables on its SAT formula is loaded in the FPGA on-chip memory. This results in less configuration effort and fewer hardware resources than other available SAT solvers. Also, we present a new approach for implementing conflict analysis based on a conflicting variables accumulator and priority encoder to determine backtrack level. Using these two new ideas, we implement an FPGA based SAT solver performing depth-first search with non-chronological conflict directed backtracking. We compare our SAT solver with other solvers through instances from DIMACS benchmarks suite