Emile Lajoinie

Post etch cleaning of low-k dielectric materials for advanced interconnects: characterization and process optimization

Abstract The removal of photoresist and etch residues from an Interlayer Dielectric sandwich incorporating a FOX (flowable oxide) low-k dielectric polymer can be successfully achieved by implementing a process using H 2 /N 2 forming gas plasma in conjunction with Posistrip ® EKC ® LE. This cleaning procedure allows W filling to be carried out without delamination and via poisoning.

Challenge of ashing and cleaning on SiOC-H dielectric: characterization and main issues

During process development of post etch cleaning for dual damascene copper/SiOC-H structures, two different kinds of new problems were faced. While a good efficiency is obviously still needed, attention must also be given to dielectric modification and photoresist poisoning which can be induced by the cleaning processes. This study examines different ways of characterization of these phenomenon.

Improved post etch cleaning for low-k and copper integration for 0.18µm technology

A key challenge for 0.18 @mm technology is the interconnect RC delay, which is the limiting factor for device performance. This delay can be reduced by the use of a low-k dielectric and copper. Some of the difficulties of integrating these interconnects are discussed, and a new strategy for post dielectric etch cleaning is presented.

Cleaning status on low-k dielectric in advanced VLSI interconnect:: Characterisation and principal issues☆

This work presents an analysis of interconnect cleaning for low-k/copper integration. Analytical data from ToF–SIMS, AES and FIB–TEM are combined to understand the mechanisms and efficacy of available cleaning chemistries in the presence of Cu and organic, Si-based, and hybrid dielectrics. The use of three different chemistry approaches is evaluated.

Resist removal process in dual damascene structure integrating Cu and SiLK® for 0.18 µm technology

As technology moves down to 0.18 @mm, the introduction of new materials such as copper and low-k dielectrics requires new process strategies. This paper addresses some issues encountered during post etch cleaning and resist removal for the integration of copper interconnects and SiLK^(R). A new safe and reliable dry/wet combination is suggested for resist removal on organic low-k dielectric / copper structures.

Improved post-etch cleaning of dual-damascene system for 0.18-μm technology

A key challenge for 0.18 micrometer technology is the interconnect RC delay time, which becomes the limiting factor for device performance. This delay can be reduced by combining the use of a material of low dielectric constant between metal lines and the use of copper, which is a better conductor than aluminum. In this paper some of the difficulties of integrating these types of interconnects are discussed, and a new strategy for post dielectric etch cleaning is presented.

Cleaning techniques for low-K dielectric materials for advanced interconnects

The removal of photoresist and etch residues from inter- metal dielectrics using SB-SOM requires new strategies in order for the dielectric constant to remain low during stripping. In this paper we examine two silsesquioxane polymers. The first, HSQ, can be successfully cleaned by implementing a process using H2/N2 plasma in conjunction with PosistripTM EKCTM LE, while the second, MSQ, can be cleaned in a unique wet step with EKC325TM.

Organic Mask Removal Assessment for 32nm Fully Depleted SOI Technology with TiN-metal Gate on HfO2

To pursue the device capability improvement, new materials have to be introduced in the gate stack. TiN metal gate on HfO2 is one of the solutions to replace existing gate. Thus, manufacturing processes, such as resist stripping, have to be adapted to these new materials as current processes can not be compatible. HfO2 compatibility was first studied by ellipsometry and ATR measurements, showing that Downstream type plasma (DS) with He-H2 or H2-N2 gas mix for dry processes, and Hydrozone ™ (HZ) for wet processes were fully compatible. Then TiN compatibility was investigated by WDXRF and XPS. Results indicate that the same processes as for HfO2 are compatible with TiN. Finally, effectiveness study proved that DS He-H2 or H2-N2 plasmas were similar to O2 plasma. To fully remove the polymers, HZ processes or derivatives have to be performed after plasmas.

Resist stripping for advanced FEOL nodes : improvements to process based on ozone diffusion by use of additives

based on ozone diffusion by use of additives Olivier Louveau, Emile Lajoinie, Olivier Pollet, Jean Philippe Odet, Sylviane Cêtre, Laurent Lachal, Béatrice Icard, Evelyne Tabouret, Marc Veillerot, Hervé Fontaine, Didier Louis. 1 STMicroelectronics, 850 rue Jean Monnet 38921 CROLLES cedex, France a Olivier.Louveau@st.com 2 Semitool, Inc, 655 W. Reserve Drive 59901 KALISPELL MT, USA 3 CEA-Leti / D2NT, 17 rue des Martyrs 38054 GRENOBLE, France

193-nm scanner characterization by SEM and electrical CD measurements

193 nm lithography is expected today to be an emerging solution for the development and the production of future integrated circuits based on sub 150 nm design rules. However the characterization and the evaluation of these tools require a lot of effort due to the 193 nm resist behavior during SEM observations. This paper presents the process flow chart to allow the evaluation of a ASM-L 5500/900 193 nm scanner by electrical measurement and the stack used for this study. After the validation of this flow chart, this work gives an overview of the ASM-L 5500/900 performances.