C. Arvet

A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (φ-Flash), suitable for full 3D integration

We present the first experimental study of a Gate-All-Around (GAA) SONOS memory architecture with 4-level crystalline nanowire channels (down to 6nm-diameter). The technology is also extended to an independent double gate memory architecture, called φ-Flash. The experimental results with 6nm nanowires show high programming windows (up to 7.4V), making the structure compatible with multilevel operation. Excellent retention even after 104 cycles is achieved. The independent double gate option has otherwise been successfully integrated with 4-level stacked nanowires for multibit applications. The φ-Flash exhibits up to 1.8V ΔVTh between its two gates, demonstrating multibits operation. The basic process to fully disconnect the different nanowires in view of a full 3D integration of a memory array is discussed.

15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET

For the first time, we report a 3D stacked sub-15 nm diameter NanoWire FinFET-like CMOS technology (3D-NWFET) with a new optional independent gate nanowire structure named PhiFET. Extremely high driving currents for 3D-NWFET (6.5 mA/mum for NMOS and 3.3 mA/mum for PMOS) are demonstrated thanks to the 3D configuration using a high-k/metal gate stack. Co-processed reference FinFETs with fin widths down to 6 nm are achieved with record aspect ratios of 23. We show experimentally that the 3D-NWFET, compared to a co-processed FinFET, relaxes by a factor of 2.5 the channel width requirement for a targeted DIBL and improves transport properties. PhiFET exhibits significant performance boosts compared to Independent-Gate FinFET (IG-FinFET): a 2-decade smaller IOFF current and a lower subthreshold slope (82 mV/dec. instead of 95 mV/dec.). This highlights the better scalability of 3D-NWFET and PhiFET compared to FinFET and IG-FinFET, respectively.

Work-function engineering in gate first technology for multi-V T dual-gate FDSOI CMOS on UTBOX

For the first time, we demonstrate low-V<inf>T</inf> (V<inf>Tlin</inf> ±0.32V) nMOS and pMOS adjusted in a gate first FDSOI technology by work-function engineering of TiN/TaAlN metal gates. Especially, for low-V<inf>T</inf> pMOS, various Chemical-Vapor-Deposited TaAlN stacks with optimized Al concentration have been studied to finely tune the work-function above midgap while maintaining good reliability and mobility. Short channel performance of 500µA/µm I<inf>ON</inf> and 245µA/µm I<inf>EFF</inf> at 2nA/µm I<inf>OFF</inf> and V<inf>DD</inf>=0.9V is reported on pMOS with a TaAlN gate. In addition, it is found that the combination of these two metal gates with either n- or p-doped ground planes below the Ultra-Thin Buried Oxide (BOX) can offer 4 different V<inf>T</inf> from 0.32V to 0.6V for both nMOS and pMOS, demonstrating a real multiple-V<inf>T</inf> capability for FDSOI CMOS while keeping the channel undoped and the V<inf>T</inf> variability around A<inf>VT</inf>=1.3mV.µm.

Localized ultra-thin GeOI: An innovative approach to germanium channel MOSFETs on bulk Si substrates

In this paper we compare two innovative approaches to the integration of Ge-channel on Insulator MOSFETs from conventional Bulk-Si substrates. The first one is based on the Ge-condensation process, and the second one relies on the epitaxy of a pure ultra-thin 2.3 nm-thick Ge layer performed directly on Si. With the second approach, we demonstrate for the first time highly-performant Localized GeOI pMOS devices down to 75 nm gate length, with controlled threshold voltage and drive current up to 600 muA/m@-1.1 V. We show a +35% improvement in drive current compared to Si references for the same Gate overdrive.

Control of Selectivity between SiGe and Si in Isotropic Etching Processes

The selectivity between SiGe and Si has been investigated in chemical dry etching. Starting from a pure CF4 process that etches SiGe with a good selectivity to Si, the modification of the gas mixture was studied with the aim of understanding the way these materials are etched in the presence of O2, N2 and/or CH2F2. Passivation phenomena were used to show that invert selectivities can be obtained. Their combination leads to ultrahigh Si:SiGe selectivity.

First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers

For the first time, a full 3D CMOS over CMOS CoolCube™ integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain. Functional 3D inverters with either PMOS or NMOS on the top level are highlighted. Furthermore, Si layer transfer above a 28nm W Metal 1 level of an industrial short loop and the return in a front end environment is presented, confirming the industrial compatibility of CoolCube™ integration.

Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

We report on vertically stacked horizontal Si NanoWires (NW) /»-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si/-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs /-FETs.

Self-Aligned Planar Double-Gate MOSFETs by Bonding for 22-nm Node, With Metal Gates, High-

In this letter, we report the fabrication and characterization of self-aligned double-gate MOSFETs with gate length down to 6 nm. Based on molecular bonding, the interest of this original process relies on the fact that, for the first time, technological options such as planar process, independently biasable gates, and metallic source and drain are integrated all together to address critical issues for sub-22-nm node, such as variability, short channel effect control, and access resistance decrease. Good electrical performance of pMOS transistors is demonstrated. Short channel effects are very well controlled down to 30 nm. The independent biasing of the two gates allows tuning of the characteristics, depending on the targeted applications.

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As technology moves down to 0.18 @mm, the introduction of new materials such as copper and low-k dielectrics requires new process strategies. This paper addresses some issues encountered during post etch cleaning and resist removal for the integration of copper interconnects and SiLK^(R). A new safe and reliable dry/wet combination is suggested for resist removal on organic low-k dielectric / copper structures.

Dielectrics, and Metallic Source/Drain

The Nano Wire (NW) CMOS technology is widely considered as a promising evolutionary solution of current FinFET technology. The main advantage of the nanowire transistors for ultimate CMOS scaling is their optimal electrostatic confinement. In this paper, the major assets of NW field-effect-transistors in leading-edge technology nodes are explained in details. For this purpose, electron (hole) transport properties of Si (SiGe) NWs and the critical contribution of strain are discussed. A particular attention is given to the key technological integration challenges to be addressed, with emphasis on the practical implementation of 3D high-density stacked-NWs architectures.