Alessio Beverina

Integration of copper with an organic low-k dielectric in 0.12-µm node interconnect

Today, copper and low-k dielectric are required to reduce interconnect delay and decrease parasitic capacitance. This paper presents the integration of copper with an organic low-k dielectric (k = 2.7) and is focused on the adaptation of the processes required when switching from SiO2 to this pure organic dielectric. After integration in a dual metal level interconnect for 0.12-µm generation, it is shown that good electrical results are obtained (100% yield for 0.4-µm pitch, via resistance > 1 Ω, capacitance reduction of 40% compared to Cu/SiO2 structures), but care must be taken when integrating this low-k material due to its low thermo-mechanical property and sensibility to moisture absorption.

High-k Gate Dielectrics on Silicon and Germanium: Impact of Surface Preparation

We review the impact of semiconductor surface preparation on the performance of metal-oxidesemiconductor field-effect transistor (MOSFET) gate stacks. We discuss high-permittivity dielectrics such as hafnium oxide and aluminum oxide on silicon and on the high carrier mobility substrate germanium. On Si, scaling of the gate stack is the prime concern. On Ge, fundamental issues of chemical and electrical passivation need to be resolved. Surface treatments considered include oxidation, nitridation, hydrogenation, chlorination, and organic functionalization.

Cleaning status on low-k dielectric in advanced VLSI interconnect:: Characterisation and principal issues☆

This work presents an analysis of interconnect cleaning for low-k/copper integration. Analytical data from ToF–SIMS, AES and FIB–TEM are combined to understand the mechanisms and efficacy of available cleaning chemistries in the presence of Cu and organic, Si-based, and hybrid dielectrics. The use of three different chemistry approaches is evaluated.

Fracture Behaviour of Pressureless Sintered Nickel-Reinforced Alumina Composites

Nickel-reinforced alumina composites have been manufactured by aqueous slip casting and pressureless sintered under flowing atmosphere of argon with 0,36 and 1% of oxygen in order to force interfacial reactions leading to the formation of a nickel-aluminum spinel. Colloidal stability of concentrated suspensions of alumina with 5, 10 and 15 vol% of nickel has been studied in terms of zeta potential, rheometry and packing density. The processed composites show a high dispersion of the nickel into the alumina matrix and green densities of 60-70 %th. The effect of sintering temperature and atmosphere on the mechanical behaviour of the composites has been investigated through Vickers indentation and fractographic SEM observations.

Barrier and Copper Seedlayer Wet Etching

This paper summarizes the process development of TiN barrier etching in presence of copper, for a thick copper level in BICMOS technology. In an industrial context, we have chosen to use a SC1 chemistry in a spin etch single wafer tool. The SC1 composition and therefore the pH level allows - the barrier to be etched with no metallic residues, ( if not clear this can be a source for shorts) - control of the selectivity between copper and TiN - control of lateral etching under copper lines, the possible source of open chains by W attack during TiN etch. The electrical results show a robust process according to current specifications, in terms of leakage and via resistance with a fresh chemistry approach. In fact, the recirculation of SC1 is not possible due to substantial concentration changes during processing, high evaporation rate of Ammonia and high decomposition rate of Peroxide in the presence of copper on surface wafer.

Advanced Surface Cleaning Strategy for 65nm CMOS Device Performance Enhancement

This paper investigates low temperature cleaning steps solutions (T°<30°) developed to enhance the 65nm transistor performance. A complete cleaning recipes optimization is realized in term of silicon consumption and defectiveness for pre-furnace clean (RCA or HFRCA), post gate etch clean PGEC (HF-SPM-SC1) and post ash clean PAC (SPM–SC1) operations. The silicon recess and the dopants consumption are reduced by using low temperature SC1 steps. Transistor drivability is improved by 8% and 7% for NMOS and PMOS respectively.