Emilio Camerlenghi

Introduction to flash memory

This paper mainly focuses on the development of the NOR flash memory technology, with the aim of describing both the basic functionality of the memory cell used so far and the main cell architecture consolidated today. The NOR cell is basically a floating-gate MOS transistor, programmed by channel hot electron and erased by Fowler-Nordheim tunneling. The main reliability issues, such as charge retention and endurance, are discussed, together with an understanding of the basic physical mechanisms responsible. Most of these considerations are also valid for the NAND cell, since it is based on the same concept of floating-gate MOS transistor. Furthermore, an insight into the multilevel approach, where two bits are stored in the same cell, is presented. In fact, the exploitation of the multilevel approach at each technology node allows an increase of the memory efficiency, almost doubling the density at the same chip size, enlarging the application range and reducing the cost per bit. Finally, NOR flash cell scaling issues are covered, pointing out the main challenges. Flash cell scaling has been demonstrated to be really possible and to be able to follow Moores law down to the 130-nm technology generations. Technology development and consolidated know-how is expected to sustain the scaling trend down to 90- and 65-nm technology nodes. One of the crucial issues to be solved to allow cell scaling below the 65-nm node is the tunnel oxide thickness reduction, as tunnel thinning is limited by intrinsic and extrinsic mechanisms.

A novel method for the experimental determination of the coupling ratios in submicron EPROM and flash EEPROM cells

A novel method for evaluating the coupling ratios alpha /sub G/ and alpha /sub D/ of hot-electron programmable memory cells has been developed. The evaluation is based only on measurements performed on the cell and does not rely on the comparison of the cell with the equivalent MOS transistor. The sensitivity to slight differences between the two structures, which becomes more severe as the scaling-down continues, is thus eliminated. The method allows the coupling ratios to be determined also in those new high-density memory array designs in which it is impossible to obtain the equivalent transistor. The method has been validated on a 0.8 mu m technology EPROM and on a 1.0 mu m technology flash-EEPROM.<<ETX>>

A 65nm NOR flash technology with 0.042/spl mu/m/sup 2/ cell size for high performance multilevel application

A 65nm NOR flash technology, featuring a true 10lambda2 , 0.042mum2 cell, is presented for the first time for 1bit/cell and 2bit/cell products. Advanced 193nm lithography, floating gate self aligned STI, cobalt salicide and three levels of copper metallization allow the integration with a high density and high performance 1.8V CMOS

Materials and Processes for Non-Volatile Memories

The development of the semiconductor industry through the CMOS technology has been possible thanks to the unique properties of the silicon and silicon dioxide material. Nevertheless the continuous scaling of the device dimension and the increase of the integration level, i.e. the capability to follow for more than 20 years the so-called Moore’s law, has been enabled not only by the Si-SiO2 system, but also by the use of other materials. The introduction of new materials every generation has allowed the integration of sub-micron and now of nanometer scale devices: different types of dielectrics, like Si3N4 or doped-SiO2, to form spacer, barrier and separation layers; conductive films, like WSi2, TiSi2, CoSi2 and NiSi2, to build low resistive gates; metals, like W, Ti, TiN, to have low resistive contacts, or like Al or Cu, to have low resistive interconnects. Although the technology development has been mainly driven by the CMOS transistor downscaling, other devices and most of all Non-Volatile Memories (NVM) have been able to evolve due to the large exploitation of these materials. NVM today represent a large portion of the overall semiconductor market and one of the most important technologies for the mobile application segment. In particular the main technology line in the NVM field is represented by the Flash Memory. Flash memory cell is based on the concept of a MOS transistor with a Floating-Gate (FG). The writing/reading operations of the cell are possible thanks again to the unique properties of the SiO2 system, being a quasi-ideal dielectric at low electric field, enabling the Flash memory to store electrons for several years, and becoming a fair conductor at higher electric field by tunnel effect, thus allowing reaching fast programming speeds. Flash have now reached the integration of many billions of bits in one monolithic component with cell dimension of 0.008um2 at 45nm technology node, always based on the FG concept. Nevertheless Flash have technological and physical constraint that will make more difficult their further scaling, even if the scaling limits are still under debate. In this contest there is the industrial interest for alternative technologies that exploit new materials and concepts to go beyond the Flash technology, to allow better scaling, and to enlarge the memory performance. Hence other technologies, alternative to floating gate devices, have been proposed and are under investigation. These new proposals exploit different physical mechanisms and different materials to store the information: magnetism and magnetoresistive materials (e.g. Co, Ni, Fe, Mn) in magnetic memories or MRAM; ferroelectricity and perovskite materials (e.g. PbTixZr1-xO3 or SrBi2Ta2O9 or BaxSr1-xTiO3) in ferroelectric memories or FeRAM; phase change and chalcogenide materials (e.g. Ge2Sb2Te5 or AsInSbTe) in phase-change memory or PCM. Among these alternative NVM, PCM are one of the most promising candidates to become a mainstream NVM, having the potentiality to improve the performance compared to Flash - random access time, read throughput, direct write, bit granularity, endurance - as well as to be scalable beyond Flash technology.