Paolo Cappelletti

Multilevel flash cells and their trade-offs

In this paper we compare six different multilevel flash cells, viz., common ground, DINOR, AND, AMG, split gate and NAND. The key conclusions are that the hot electron effect lends itself better than tunneling as the multilevel programming mechanism. The common ground cell is the most suitable for multilevel flash cells. The NAND architecture is the least favorable.

Failure mechanisms of flash cell in program/erase cycling

The impact of program/erase cycling on flash memory cell is reviewed considering both performance degradation of the typical bit and the evolution of the erase threshold voltage distribution of the whole memory array. Emphasis is given to the failure mechanisms which affect flash memory endurance: the erratic erase phenomenon is discussed with reference to the model recently reported in the literature and a new degradation mechanism, induced by parasitic drain stress conditions in program/erase cycling, is presented.<<ETX>>

Flash Memory Reliability

With reference to the mainstream technology, the most relevant failure mechanisms which affect yield and reliability of Flash memory are reviewed, showing the primary role played by tunnel oxide defects. The effectiveness of a good test methodology combined with a proper product design for screening at wafer sort latent defects of tunnel oxide is highlighted as a key factor for improving Flash memory reliability. The degradation of device performance induced by program/erase cycling is discussed, covering both the behaviour of a typical cell and the evolution of memory array distribution. The erratic erasure phenomenon is illustrated as the most relevant mechanism reported so far to cause single bit failures in endurance tests. Finally, reliability implications of multilevel cell concepts are briefly analysed.

Experimental transient analysis of the tunnel current in EEPROM cells

Since the cell is written with a ramp waveform pulse in order to minimize the maximum tunnel current in actual device operation, the measurements were performed with ramp waveform writing pulses at different ramp speeds. The kind of information obtained from the transient analysis greatly improves the understanding of the device physics. By measuring tunnel current, some expected results, such as the dependence of the maximum current value on the ramp speed, were observed. Some unexpected results, such as an anomalous peak during the erasing operation and the influence of the ramp speed on the conduction properties of the thin oxide, which is shown by the Fowler-Nordheim plot of the experimental tunnel current, were also observed. >

Accelerated current test for fast tunnel oxide evaluation (of EPROMs)

An accelerated method for wafer-level tunnel oxide evaluation and screening is proposed and compared to the widely used constant current test. The dielectric is stressed by an exponentially increasing current flow until breakdown occurs. In a short measurement time a wide current density range is explored, so that both latent defectivity and intrinsic oxide properties can be monitored. It is concluded that sensitivity in charge to breakdown determination and its good correlation with constant current stress results make the ramped current method suitable for routine use in both R&D and production.<<ETX>>

What we have learned on flash memory reliability in the last ten years

In this paper we report the most important progresses on flash memory reliability in the last decade. The capability of mastering the degradation mechanisms, mainly related to the generation of localized defects in the tunnel oxide during writing operations, comes from the large know-how developed in more that 20 years of research and industrial activity.

Wafer level tunnel oxide reliability evaluation by means of the Exponentially Ramped Current Stress method

Abstract The Exponentially Ramped Current Stress method (ERCS) is an accelerated test for wafer-level tunnel oxide evaluation and screening. In this work the technique is described and its advantages are discussed, with special attention to the comparison with the most widely used constant current test. In the ERCS the dielectric is stressed by an exponentially increasing current flow until breakdown occurs. In a short measurement time a wide current density range is explored, so that both defectivity and intrinsic oxide properties can be monitored. The intrinsic charge-to-breakdown dependence on capacitor area and on current density under constant current stress have also been investigated, both for gate and for substrate charge injection. A simple algorithm is proposed in order to correlate the two techniques, allowing for the projection of the results obtained with the ERCS method to constant current stress conditions. The self-consistency of such an algorithm has been verified on the base of independent experimental results. It is concluded that the Exponentially Ramped Current Stress is suitable both as an efficient tool in Research and Development and as a routine control in production; in fact, the method shows several desirable qualities, such as the short measurement time, the good sensitivity in charge to breakdown determination over a wide range, the good correlation with constant current stress results, as well as the possibility of other electrical parameter extraction (i.e. Fowler-Nordheim characteristics, breakdown electric field, Time Dependent Dielectric Breakdown).

Application of advanced ion implantation techniques to Flash memories

Abstract Flash memories have become the most important of non-volatile memories because of their potential application as mass storage devices in portable computers. The evolution of Flash memory technology is oriented to both reducing cell size and up-grading product functions. Significant modifications of the structure and the operating modes of memory cell as well as innovative CMOS process architectures are needed for next generations of Flash memories. An important contribution to the evolution of Flash technology comes from the implementation of advanced ion implantation techniques; the role of large angle tilted implantation and of high energy implantation is illustrated showing most relevant applications in relation with the improvements of device structure and performance.