Emily Fisch

Inspection of EUV reticles

This paper presents the results of patterned and unpatterned EUV mask inspections. We will show inspection results related to EUV patterned mask design factors that affect inspection tool sensitivity, in particular, EUV absorber material reflectivity, and EUV buffer layer thickness. We have used a DUV (257nm) inspection system to inspect patterned reticles, and have achieved defect size sensitivities on patterned reticles of approximately 80 nm. We have inspected EUV substrates and blanks with a UV (364nm) tool with a 90nm to a 120 nm PSL sensitivity, respectively, and found that defect density varies markedly, by factors of 10 and more, from sample to sample. We are using this information in an ongoing effort to reduce defect densities in substrates and blanks to the low levels that will be needed for EUV lithography. While DUV tools will likely meet the patterned inspection requirements of the 70 nm node in terms of reticle defect sensitivity, wavelengths shorter than 200 nm will be required to meet the 50 nm node requirements. This research was sponsored in part by NIST-ATP under KLA-Tencor Cooperative Agreement #70NANB8H44024.

STI TEOS densification for furnaces and RTP tools

The traditional oxide densification anneal used to reduce the etch rate of TEOS relative to thermal oxide is inadequate for high-aspect ratio shallow trench isolation processes. Excessive removal of TEOS during wet oxide etches causes yield detractors such as seams (resulting in gate-to-gate shorts), divots (increasing corner leakage), and global TEOS pulldown (creating unwanted topography). Therefore, an alternative densification process was developed. In addition to the defect and device issues, there was incentive to develop a rapid thermal process (RTP) to reduce cycle time. This paper summarizes our work to improve the TEOS anneal process. The etch rate work on monitor wafers compares densification under furnace and RTP conditions for several different ambients and temperatures. The influence of wafer location in the furnace and of film variations through depth is also evaluated. Additionally, after an effective anneal process was extracted from the initial monitor work, it was implemented on 0.25 /spl mu/m CMOS and DRAM technologies in manufacturing. Electrical and physical data were used to evaluate the effectiveness of the anneal.

Chrome dry etching for 65-nm node mask manufacturing

A new chrome etch system was acquired and implemented to manufacture 65 nm node critical level masks. The etch performance of FEP 171, ZEP 7000, NEB 22, and REAP 200 resist systems in this new chrome etch system was evaluated. The critical dimension (CD) uniformity, etch bias, and etch linearity of this new etch system relative to the older generation etch system is presented. Implementation of the new etch system resulted in a 40-60 nm reduction in etch bias with no degrade in CD uniformity performance. In addition, it was found that the etch contribution to CD linearity was reduced by 50%. Detailed characterization of both macroloading and microloading etch effects was performed and showed substantial improvement relative to the previous generation etch system. The change in chrome etch rate as a function of etch area was reduced by 50%, improving mean to target CD performance on new designs. Implementation of the new etch system has enabled achievement of CD and defect density performance requirements for 65 nm node mask manufacturing. The results presented in this paper were collected during the process development phase and are not necessarily representative of the final optimized process.

Low-defect EUVL multilayers on standard-format mask blanks

Fabrication of low defect density mask blanks remains as one of the key challenges to commercialization of Extreme Ultraviolet Lithography (EUVL). A low defect deposition process for EUV-reflective Mo/Si multilayers has been developed on 200mm silicon substrates because of the availability of sensitive, fast defect inspection tools for wafers. A defect level of 0.05 defects/cm2 at 90 nm defect size detection threshold can now be achieved repeatedly on wafers. We upgraded the low defect multilayer deposition (LDD) system to allow coating of standard format 152mm square mask blanks. Mask blank defect inspection was performed at IBM with a typical sensitivity of 100 nm PSL equivalent. We used the single reticle SMIF pod (RSP) standard both for clean, automated handling and for shipping of the mask substrates and blanks. The added defect level during shipping was improved to 0.02 defects/cm2. We achieved a process-added defect density of 0.38 defects/cm2 on a lot of 5 blanks, which was the same defect level as on wafers coated before and after the blanks. We also improved the reflectance and thickness control on blanks to achieve 66.5% EUV reflectance, and a thickness uniformity of 0.07% P-V or 0.04% rms. The improved reflectance and uniformity meet the SEMI P38 specifications for EUVL mask blanks. We have discovered no differences in defect levels or film quality in the coating of standard square format as compared to silicon wafers.

Process for improved reflectivity uniformity in extreme-ultraviolet lithography (EUVL) masks

Fabrication of EUVL masks requires formation of both a repair buffer layer and an EUV absorber layer on top of a molybdenum/silicon (Mo/Si) multilayer coated mask blank. Alteration of the Mo/Si multilayer during etch, repair or cleaning of the EUVL mask can be detrimental to the reflectivity and thus the functionality of the final mask. IBM’s Next Generation Lithography (NGL) group has reported on EUVL mask fabrication based on an absorber of low stress chromium (Cr) and a buffer layer of silicon dioxide (SiO2). Due to poor etch selectivity between SiO2 and the underlying silicon capping layer, the finished masks had non-uniform and reduced EUV reflectivity after processing. This led to the development of an alternative absorber stack combination of an absorber layer of low stress TaNx on a buffer layer of low stress Cr. This paper describes the improved reflectivity uniformity of this type of mask along with several aspects of mask quality, such as CD control and image placement.

EUVL mask fabrication for the 45-nm node

The extreme ultraviolet lithography (EUVL) mask differs from its predecessors in many ways. The most significant change is that the EUVL mask is reflective, introducing many new film layers and mask sensitivities. An additional complication is the small linewidths associated with the 45-nm node that is targeted for EUVL mask introduction. This paper concentrates on the physical specifications associated with the 45-nm node EUVL mask. Relative to current masks, the defect levels must be lower and the film quality must be higher. Standard cleans may be incompatible with new mask requirements. To understand the development requirements, the cleaning efficiency, film removal, film roughness, defect levels and film reflectivity are quantified on both EUVL mask film monitors and EUVL masks. Target specifications and measured properties of the 45-nm node masks will be compared.

Aids for driving lithography hard: wafer-level process control features

This paper investigates the design of targets for in-line lithography process control. The need for wafer-level understanding and control of defocus has driven the development of several of methods for detecting focus shifts. The methods are typically based on measurements of line-end shortening and use optical methods. This work starts a dual-tone pair of arrays, one built from resist lines and the other from resist troughs. These process control targets area also known as schnitzls. The influence of the shape of the individual lines, the line pitch and separation of arrays are investigated using both simulations and wafer resist CDSEM measurements. A theoretical model was applied to all data to enable objective comparison of different designs. A guide to dose and defocus target design for process window monitoring is provided as part of the summary.

Exploring advanced mask repair options

The extension of 193 nm lithography to the 65 and 45nm nodes transfers the development challenges from those associated with a new wavelength to those required to push an existing technology further. With respect to mask repair, new challenges are introduced as the mask features shrink and OPC becomes increasingly aggressive. These same factors increase mask costs to provide strong motivation for enhancing existing repair capabilities. The business case for investing in repair has only become stronger for leading edge 193 nm masks. This paper evaluates several repair techniques on a range of clear and opaque defects in Cr, MoSi and quartz features. A systematic approach is used to evaluate options for understanding the quality of a repair. Though conventional reconstruction techniques are used, we also explore non-intuitive repairs. These non-standard repairs attempt to reconstruct the printed image without duplicating the designed physical structure. An understanding of each methods process latitude is gained. AIMS analysis, lithographic simulations, and wafer print results are used to refine the understanding of repair specifications.

Status of fabrication of square format masks for extreme ultraviolet lithography (EUVL) at the MCoC

Fabricating masks for extreme ultraviolet lithography is challenging. The high absorption of most materials at 13.4 nm and the small critical dimension (45 nm) at the target insertion node force many new features, including reflective mask design, new film choices, and stringent defect specifications. Fabrication of these masks requires the formation and patterning of both a repair buffer layer and an EUV absorber layer on top of a molybdenum/silicon multi-layer substrate. IBM and Photronics have been engaged in developing mask processing technology for x-ray, electron beam projection and extreme ultraviolet lithographies at the Next Generation Lithography Mask Center of Competency (NGL-MCoC) within IBMs mask facility at Essex Junction, Vermont. This paper describes recent results of mask fabrication on 6 x 6 x 1/4 inch EUVL substrates (quartz with molybdenum silicon multi-layers) at the MCoC. Masks fabricated with high and low-stress chromium and externally deposited chromium absorber films are compared. In particular, etch characteristics, image size, image placement, line edge roughness, and defect levels are presented and compared. Understanding the influence of the absorber film characteristics on these parameters will enable us to optimize the effectiveness of a given absorber film or to select acceptable alternatives.

EPL mask fabrication

The next generation lithography, either electron or photon based, will be first introduced on critical levels for device manufacture. These levels have different requirements for difficulty of meeting image size uniformity, image placement, and patterning requirements on masks. Membrane masks are needed for electron projection lithography (EPL), and the fabrication of membrane masks generates new requirements such as the need for complementary mask pairs for stencil masks. In this paper, we discuss experiments for fabricating EPL masks for device levels.