Eng Fong Chor

Enhanced device performance of AlGaN/GaN HEMTs using HfO2 high-k dielectric for surface passivation and gate oxide

AlGaN/GaN high electron mobility transistors (HEMTs) using HfO2 as a surface passivation layer and metal–oxide–semiconductor HEMTs (MOS-HEMTs) using HfO2 as gate oxide have been investigated and compared with the regular HEMTs. In MOS-HEMTs, the HfO2 gate dielectric is also used for passivation simultaneously. Our measurements have shown that both passivated HEMTs and MOS-HEMTs outperformed the regular HEMTs in dc, high-frequency and pulsed-mode operations, with MOS-HEMTs exhibiting the best characteristics, including the highest drain current, the lowest gate leakage current, the largest gate voltage swing, the highest cut-off frequencies and the best immunity to current collapse. In addition, the decrease in transconductance of MOS-HEMTs relative to HEMTs is as low as 8.7%, most probably a consequence of the high-k value of HfO2. Our results thus indicate the great potential of HfO2/AlGaN/GaN MOS-HEMTs for high-frequency and high-power applications.

A propagation-delay expression and its application to the optimization of polysilicon emitter ECL processes

A sensitivity analysis is used to compute an analytical expression for the propagation delay of an emitter-coupled logic (ECL) gate in terms of the electrical parameters of the circuit. These electrical parameters are in turn related to the processing parameters through approximate analytical equations and computer simulation programs. In this way, a simple means is evolved of optimizing an ECL process for maximum circuit speed. The accuracy of the propagation-delay expression and the related equations for the electrical parameters are verified by comparison with experimental results on 6- mu m geometry circuits. By means of the propagation-delay expression, it is shown that the optimum propagation delay at 6- mu m geometry is 320 ps for a conventional process and 160 ps for a self-aligned process. On scaling to a geometry of 0.5 mu m, a propagation delay of 20 ps is predicted for a fully optimized self-aligned process. >

Transparent indium zinc oxide ohmic contact to phosphor-doped n-type zinc oxide

Transparent indium zinc oxide (IZO) ohmic contacts to phosphor-doped n-type ZnO have been formed. The resistance, transmittance, and phase reliability of the contacts were investigated. As deposited, an ohmic contact was formed with a specific contact resistance of about 1.1×10−4Ωcm2 and the transmittance of the ZnO∕IZO (520∕350nm) film was more than 75% in the 450–1100nm wavelength range. After annealing at 400°C for 5min in a vacuum (2×10−5mbar), the specific contact resistance was reduced by about two orders of magnitude to 3.8×10−6Ωcm2, while maintaining the contact stability and high optical transparency.

Tuning the Schottky barrier height of nickel silicide on p-silicon by aluminum segregation

We report the Schottky barrier height (SBH) tuning at the nickel silicide (NiSi)∕p-Si junction by the introduction of aluminum (Al) using ion implantation and its segregation after silicidation. The SBH for holes has been found to decrease with increasing concentration of Al at the NiSi∕p-Si interface. We demonstrate the achievement of one of the lowest reported SBH for holes of 0.12eV, with less than 0.1at.% Al in NiSi, which is promising for application in p-channel Schottky source/drain transistors.

Emitter resistance of arsenic- and phosphorus-doped polysilicon emitter transistors

Measurements of emitter resistance have been made on arsenic- and phosphorus-doped polysilicon emitter bipolar transistors, fabricated with or without an interfacial oxide layer. It is found that the emitter resistance of phosphorus-doped transistors is considerably lower than that of arsenic-doped transistors. In addition the presence of a deliberately grown interfacial oxide layer leads to a significant increase in emitter resistance for both arsenic- and phosphorus-doped devices.

Properties of p-type and n-type ZnO influenced by P concentration

The electrical conductivity of P-doped ZnO can be controlled by changing the P-doping concentration. With increasing P concentration, ZnO can be changed from n type to p type. At the same time, a redshift of the band gap energy is observed by using the photoluminescence spectroscopy and UV-visible spectrophotometer. X-ray diffraction results show that lattice spacings of ZnO increase with P concentration, which indicates that P substitutes O, and this leads to a lattice spacing increase and an optical band gap energy decrease.

Electrical characterization and metallurgical analysis of Pd-containing multilayer contacts on GaN

Ti(250 A)/Al(2200 A)/Pd(600 A)/Au(1600 A) contact on aqua-regia surface treated n-GaN (Si∼1.0×1019 cm−3) has yielded a minimum specific contact resistance (ρc) of 4.21×10−8 Ω cm2, achieved after thermal annealing at 500 °C for 8 min. This is superior to the most common n-GaN contact, Ti/Al, which has also been studied in the current work and produced a lowest ρc of 4.63×10−6 Ω cm2, obtained after annealing at 700 °C for 2 min. The long-term thermal stability analysis has also revealed that the Ti/Al/Pd/Au contact is more stable than Ti/Al on n-GaN. The projected mean time to 50% increase in ρc(μ50) at 150 °C for the former is 1.22×1012 h, which is higher by about three orders of magnitude than that of the latter at 3.54×109 h. Pd(200 A)/Ni(300 A)/Au(2000 A) contact on boiling aqua-regia surface treated p-GaN (Mg∼1.0×1018 cm−3) has also been investigated and demonstrated a reasonable ohmic behavior with a ρc of 5.03×10−4 Ω cm2 after thermal annealing at 450 °C for 2 min. However, its thermal stability is m...

Electrical characterization, metallurgical investigation, and thermal stability studies of (Pd, Ti, Au)-based ohmic contacts

Although Pd/Ti/Pd/Au contacts are similar to their Pt/Ti/Pt/Au counterparts in providing low specific contact resistance, ρc, the former exhibits long-term thermal stability. Their projected mean times to 50% increase in ρc(μ50) at 150 °C to p+-GaAs (⩾3.43×1015 h) are higher than those of the latter by over five orders of magnitude. Contacts to p+-In0.53Ga0.47As are not as thermally stable, with a much lower albeit respectable μ50 at 150 °C of ⩾2.25×105 h. Contacts with an interfacial Pd layer provide ρc’s that are at least two times lower than those without, and the presence of an oxide layer (GaxTiyOz) at the Ti/GaAs interface is identified as a possible cause. Pd–Ga–As phases are formed at the Pd/GaAs interface, being As-rich (PdxGayAs) initially and convert to Ga-rich phases (PduGavAs) upon a high temperature anneal and the eventual composition depends on the evaporated interfacial Pd thickness and annealing conditions. This could probably explain the existence of an optimum interfacial Pd layer thick...

Pulsed laser annealing of Be-implanted GaN

Postimplantation thermal processing of Be in molecular-beam-epitaxy-grown GaN by rapid thermal annealing (RTA) and pulsed laser annealing (PLA) was investigated. It has been found that the activation of Be dopants and the repair of implantation-induced defects in GaN films cannot be achieved efficiently by conventional RTA alone. On the other hand, good dopant activation and surface morphology and quality were obtained when the Be-implanted GaN film was annealed by PLA with a 248nm KrF excimer laser. However, observations of off-resonant micro-Raman and high-resolution x-ray-diffraction spectra indicated that crystal defects and strain resulting from Be implantation were still existent after PLA, which probably degraded the carrier mobility and limited the activation efficiency to some extent. This can be attributed to the shallow penetration depth of the 248nm laser in GaN, which only repaired the crystal defects in a thin near-surface layer, while the deeper defects were not annealed out well. This situ...

Strong Low-Frequency Noise in Polysilicon Emitter Bipolar Transistors with Interfacial Oxide due to Fluctuations in Tunneling Probabilities

Strong 1/fα (2>α>1) noise was observed in polysilicon emitter bipolar transistors with an interfacial oxide layer sandwiched between the polysilicon and monocrystalline silicon emitter regions but not in similar transistors without interfacial oxide. The noise was explained as fluctuations in the carrier tunneling probabilities through the interfacial oxide. A simple equivalent circuit was proposed to model the strong 1/fα noise.