Lap Chan

Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction

The device physics and guiding principles for the design of the double-gate tunneling field-effect transistor with silicon-germanium (SiGe) heterojunction source are discussed. Two dimensional device simulations were employed to study the influence of the position of the SiGe∕Si heterojunction on band-to-band tunneling and device performance. It is established that band-to-band tunneling occurs at a distance of ∼4nm from the gate edge in the source region. In order for the narrower bandgap of SiGe to play a dominant role, the overlap between the SiGe region and the gate should be such that the whole tunneling path of the electrons is located in SiGe. To harness the maximum benefits of the high band-to-band tunneling rate in SiGe, an overlap of ∼2nm between the SiGe region and the gate would be required.

Device Design and Scalability of a Double-Gate Tunneling Field-Effect Transistor with Silicon–Germanium Source

A novel double-gate (DG) tunneling field-effect transistor (TFET) with silicon–germanium (SiGe) Source is proposed to overcome the scaling limits of complementary metal–oxide–semiconductor (CMOS) technology and further extends Moores law. The narrower bandgap of the SiGe source helps to reduce the tunneling width and improves the subthreshold swing and on-state current. Less than 60 mV/decade subthreshold swing with extremely low off-state leakage current is achieved by optimizing the device parameters and Ge content in the source. For the first time, we show that such a technology proves to be viable to replace CMOS for high performance, low standby power, and low power technologies through the end of the roadmap with extensive simulations.

Sub-0.1-eV Effective Schottky-Barrier Height for NiSi on n-Type Si (100) Using Antimony Segregation

We report a new method of forming nickel silicide (NiSi) on n-Si with low contact resistance, which achieves a Schottky barrier height of as low as 0.074 eV. Antimony (Sb) and nickel were introduced simultaneously and annealed to form NiSi on n-Si (100). Sb dopant atoms were found to segregate at the NiSi/Si interface. The devices with Sb segregation show complete nickel monosilicide formation on n-Si (100) and a close-to-unity rectification ratio. The rectification ratio Rc is defined to be the ratio of the forward current to the reverse current, where the forward and reverse currents are measured using forward and reverse bias voltages, respectively, having the same magnitude of 0.5 V. This process is also compatible and easily integrated in a CMOS fabrication process flow.

Low Schottky barrier height for silicides on n-type Si (100) by interfacial selenium segregation during silicidation

The electron Schottky barrier height ΦBn modulation for NiSi and PtSi formed on selenium-implanted n-type Si (100) has been experimentally investigated. Selenium (Se) segregation is observed at the silicide/n-Si(100) interface during silicidation process. ΦBn of 83 and 120 meV were achieved for Se segregated NiSi and PtSi on n-Si (100) interfaces, respectively. Contrary to previously reported Fermi level depinning effect in monolayer Se-passivated n-Si (100), the low ΦBn achieved in this work points to metal silicide Fermi level pinning near to conduction band EC of n-Si (100).

I-MOS Transistor With an Elevated Silicon–Germanium Impact-Ionization Region for Bandgap Engineering

An impact-ionization MOS (I-MOS) transistor with an elevated impact-ionization region (I-region) and excellent subthreshold swing of 3.2 mV/dec at room temperature is demonstrated. An elevated Si_0.75Ge_0.25 region is integrated and employed to engineer the bandgap and impact-ionization rate in the I-region. Compared to a device with a Si I-region, an I-MOS device with a Si_0.75Ge _0.25 I-region shows significantly enhanced performance due to the smaller bandgap of the I-region and the enhanced impact-ionization rate. For the I-MOS device with a Si_0.75Ge_0.25 I-region, the breakdown voltage is also reduced, and a significant drive current enhancement is achieved at V_G-V_T=1 V and a gate length of 80 nm

A novel CMOS compatible L-shaped impact-ionization MOS (LI-MOS) transistor

This paper reports a novel L-shaped impact-ionization MOS (LI-MOS) transistor technology that achieves subthreshold swing well below 60 mV/decade at room temperature. First, the LI-MOS transistor is CMOS process compatible, and requires little process modification for integration in a manufacturable process. Second, the LI-MOS structure employs raised source/drain (S/D) regions that enable controllability and scalability of the impact ionization region (I-region). Third, the LI-MOS has superior compactness over previously reported I-MOS device structures. Fourth, the LI-MOS enables the integration of novel materials for band gap and strain engineering to enhance the impact ionization rate in the I-region. Based on the above technology, we demonstrate a record subthreshold swing of 4.5 mV/decade at room temperature for a 100 run gate length device that incorporates a SiGe I-region. The smallest impact-ionization-based MOS device with a gate length of 60 nm is also demonstrated with a subthreshold swing that is well below 60 mV/decade

Silicon–Carbon Stressors With High Substitutional Carbon Concentration and In Situ Doping Formed in Source/Drain Extensions of n-Channel Transistors

We report the first demonstration of n-channel field-effect transistors (N-FETs) with in situ phosphorus-doped silicon-carbon (SiCP) stressors incorporated in the source/drain extension (SDE) regions. A novel process which formed recessed SDE regions followed by selective epitaxy of SiCP was adopted. High in situ doping contributes to low series resistance to channel resistance ratio and is important for reaping the benefits of strain. Substitutional carbon concentration was varied, showing enhanced drive current with increased for comparable off-state leakage, series resistance, and control of short-channel effects. A record high carbon substitutional concentration of 2.1% was achieved. Use of heavily doped silicon-carbon stressor with large lattice mismatch with respect to Si and placed in close proximity to the channel region in the SDE regions is expected to be important for strain engineering in nanoscale N-FETs.

Performance enhancement of n-channel impact-ionization metal-oxide-semiconductor transistor by strain engineering

The introduction of lattice strain in impact-ionization metal-oxide-semiconductor (I-MOS) transistors for performance enhancement is reported. Lattice strain affects impact ionization and its impact on device performance is explained in relation to the physics of I-MOS device operation. By integrating epitaxial silicon-carbon (Si0.99C0.01) source and drain regions in a complementary-MOS-compatible fabrication process, strained n-channel I-MOS devices were fabricated. Tensile strain in the channel and impact-ionization regions contributes to enhanced electron transport and device characteristics. The strained I-MOS technology demonstrates an excellent subthreshold swing of 5.3mV∕decade at room temperature. Compared to control I-MOS devices with Si raised source/drain, strained I-MOS devices show significantly higher drive current and a steeper subthreshold swing.

A Double-Spacer I-MOS Transistor With Shallow Source Junction and Lightly Doped Drain for Reduced Operating Voltage and Enhanced Device Performance

In this letter, a double-spacer (DS) design is utilized for the formation of shallow source and lightly doped drain to further optimize the impact-ionization MOS (I-MOS) transistor structure. The breakdown voltage VBD needed for avalanche breakdown is lowered due to the shallow source extension. With the formation of the lightly doped drain extension, the impact of drain bias on breakdown voltage, and hence, the threshold voltage VT is also reduced. The DS I-MOS is fabricated and characterized. Detailed analysis and physical explanation of the impact of drain/gate bias on the device characteristics are provided. Compared to the conventional I-MOS transistor, the shallow source extension reduces the breakdown voltage [drain-induced breakdown voltage lowering (DIBVL)] by 0.3-0.6 V, and the lightly doped drain extension reduces the DIBVL up to 0.17 V/V. In addition, excellent subthreshold swing and good device performance are achieved.

Simulation and design of a germanium L-shaped impact-ionization MOS transistor

This paper reports a novel L-shaped impact-ionization MOS (LI-MOS) transistor structure that achieves a subthreshold swing of well below 60 mV/decade at room temperature and operates at a low supply voltage. The device features an L-shaped or an elevated impact-ionization region (I-region), which displaces the hot carrier activity away from the gate dielectric region to improve hot carrier reliability and VT stability problems. Germanium, which has a lower bandgap and impact-ionization threshold energy lower than silicon, is chosen as the material of choice for the LI-MOS transistor structure. Device physics and design principles for the LI-MOS transistor are detailed through extensive two-dimensional device simulations. The LI-MOS transistor exhibits excellent scalability, making it suitable for augmenting the performance of standard CMOS transistors in future technology generations.