Enric Pastor

Petri Net Analysis Using Boolean Manipulation

This paper presents a novel analysis approach for bounded Petri nets. The net behavior is modeled by boolean functions, thus reducing reasoning about Petri nets to boolean calculation. The state explosion problem is managed by using Binary Decision Diagrams (BDDs), which are capable to represent large sets of markings in small data structures. The ability of Petri nets to model systems, the flexibility and generality of boolean algebras, and the efficient implementation of BDDs, provide a general environment to handle a large variety of problems. Examples are presented that show how all the reachable states (1018) of a Petri net can be efficiently calculated and represented with a small BDD (103 nodes). Properties requiring an exhaustive analysis of the state space can be verified in polynomial time in the size of the BDD.

Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets

This paper presents a methodology for the verification of speed-independent asynchronous circuits against a Petri net specification. The technique is based on symbolic reachability analysis, modeling both the specification and the gate-level network behavior by means of boolean functions. These functions are efficiently handled by using Binary Decision Diagrams. Algorithms for verifying the correctness of designs, as well as several circuit properties are proposed. Finally, the applicability of our verification method has been proven by checking the correctness of different benchmarks.

Symbolic analysis of bounded Petri nets

This paper presents a symbolic approach for the analysis of bounded Petri nets. The structure and behavior of the Petri net is symbolically modeled by using Boolean functions, thus reducing reasoning about Petri nets to Boolean calculation. The set of reachable markings is calculated by symbolically firing the transitions in the Petri net. Highly concurrent systems suffer from the state explosion problem produced by an exponential increase of the number of reachable states. This state explosion is handled by using Binary Decision Diagrams (BDDs) which are capable of representing large sets of markings with small data structures. Petri nets have the ability to model a large variety of systems and the flexibility to describe causality, concurrency, and conditional relations. The manipulation of vast state spaces generated by Petri nets enables the efficient analysis of a wide range of problems, e.g., deadlock freeness, liveness, and concurrency. A number of examples are presented in order to show how large reachability sets can be generated, represented, and analyzed with moderate BDD sizes. By using this symbolic framework, properties requiring an exhaustive analysis of the reachability graph can be efficiently verified.

Checking signal transition graph implementability by symbolic BDD traversal

This paper defines conditions for a Signal Transition Graph to be implemented by an asynchronous circuit. A hierarchy of the implementability classes is presented. Our main concern is the implementability of the specification under the restricted input-output interface between the design and the environment, i.e., when no additional interface signals are allowed to be added to the design. We develop algorithms and present experimental results of using BDD-traversal for checking STG implementability. These results demonstrate efficiency of the symbolic approach and show a way of improving existing tools for STG-based asynchronous circuit design.<<ETX>>

A middleware architecture for unmanned aircraft avionics

An Unmanned Aerial Vehicle is a non-piloted airplane designed to operate in dangerous and repetitive situations. With the advent of UAVs civil applications, UAVs are emerging as a valid option in commercial scenarios. If it must be economically viable, the same platform should implement a variety of missions with little reconfiguration time and overhead. This paper presents a middleware-based architecture specially suited to operate as a flexible payload and mission controller in a UAV. The system is composed of low-cost computing devices connected by network. The functionality is divided into reusable services distributed over a number of nodes with a middleware managing their lifecycle and communication. Some research has been done in this area; yet it is mainly focused on the control domain and in its realtime operation. Our proposal differs in that we address the implementation of adaptable and reconfigurable unmanned missions in low-cost and low-resources hardware.

Requirements, Issues, and Challenges for Sense and Avoid in Unmanned Aircraft Systems

The sense and avoid capability is one of the greatest challenges that has to be addressed to safely integrate unmanned aircraft systems into civil and nonsegregated airspace. This paper gives a review of existing regulations, recommended practices, and standards in sense and avoid for unmanned aircraft systems. Gaps and issues are identified, as are the different factors that are likely to affect actual sense and avoid requirements. It is found that the operational environment (flight altitude, meteorological conditions, and class of airspace) plays an important role when determining the type of flying hazards that the unmanned aircraft system might encounter. In addition, the automation level and the data-link architecture of the unmanned aircraft system are key factors that will definitely determine the sense and avoid system requirements. Tactical unmanned aircraft, performing similar missions to general aviation, are found to be the most challenging systems from an sense and avoid point of view, and further research and development efforts are still needed before their seamless integration into nonsegregated airspace

Wildfire monitoring using a mixed air-ground mobile network

Forest fires are a challenging problem for many countries. They often cause economical lost and ecological damage, and they can sometimes even cost human lives. Finding hot spots immediately after a fire is an important part of fighting forest fires. The main objective is to obtain a temperature map of the burned area, to locate the most critical embers. This information can help firefighter managers make the correct decisions about ground crew movements. The pervasive application described in this article lets firefighters obtain images of hot spots directly from an unmanned aircraft and receive commands from their manager through a communication network. Every firefighter holds a personal electronic device (PED), which includes a touch screen, Wi-Fi connectivity, a GPS receiver, and temperature sensors. Because terrain conditions such as abrupt ravines, rocks, and dense vegetation can introduce obstacles to connectivity, a balloon with a Wi-Fi device is tethered to every firefighters truck to improve communication. In addition, a fixed-wing unmanned aircraft augments the number of communication layers to three. This article studies the quality of this three-layered network in maintaining the applications bandwidth requirements.

Formal verification of safety properties in timed circuits

The incorporation of timing makes circuit verification computationally expensive. This paper proposes a new approach for the verification of timed circuits. Rather than calculating the exact timed stare space, a conservative overestimation that fulfills the property under verification is derived. Timing analysis with absolute delays is efficiently performed at the level of event structures and transformed into a set of relative timing constraints. With this approach, conventional symbolic techniques for reachability analysis can be efficiently combined with timing analysis. Moreover the set of timing constraints used to prove the correctness of the circuit can also be reported for backannotation purposes. Some preliminary results obtained by a naive implementation of the approach show that systems with more than 10/sup 6/ untimed states can be verified.

Decomposition and technology mapping of speed-independent circuits using Boolean relations

Presents a new technique for the decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available in the design library. The proposed method iteratively performs Boolean decomposition of each such gate F into a two-input combinational or sequential gate G, which is available in the library, and two gates H/sub 1/ and H/sub 2/, which are simpler than F, while preserving the original behavior and speed-independence of the circuit. To extract functions for H/sub 1/ and H/sub 2/, the method uses Boolean relations, as opposed to the less powerful algebraic factorization approach used in previous methods. After logic decomposition, overall library matching and optimization is carried out. Logic resynthesis, performed after speed-independent signal insertion for H/sub 1/ and H/sub 2/, allows for the sharing of decomposed logic. Overall, this method is more general than existing techniques based on restricted decomposition architectures, and thereby leads to better results in technology mapping.

A structural encoding technique for the synthesis of asynchronous circuits

This paper presents a method for the automatic synthesis of asynchronous circuits from Petri net specifications. The method is based on a structural encoding of the system in such a way that a circuit implementation is always guaranteed. Moreover, a set of transformations is presented for the subclass of Free-Choice Petri nets that enables the exploration of different solutions. All transformations preserve the property of free-choiceness, thus enabling the use of structural methods for the synthesis of asynchronous circuits. Preliminary experimental results indicate that the quality of the circuits is comparable to that obtained by methods that require an exhaustive enumeration of the state space. This novel synthesis method opens the door to the synthesis of large control specifications generated from hardware description languages.