Oriol Roig

Petri Net Analysis Using Boolean Manipulation

This paper presents a novel analysis approach for bounded Petri nets. The net behavior is modeled by boolean functions, thus reducing reasoning about Petri nets to boolean calculation. The state explosion problem is managed by using Binary Decision Diagrams (BDDs), which are capable to represent large sets of markings in small data structures. The ability of Petri nets to model systems, the flexibility and generality of boolean algebras, and the efficient implementation of BDDs, provide a general environment to handle a large variety of problems. Examples are presented that show how all the reachable states (1018) of a Petri net can be efficiently calculated and represented with a small BDD (103 nodes). Properties requiring an exhaustive analysis of the state space can be verified in polynomial time in the size of the BDD.

Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets

This paper presents a methodology for the verification of speed-independent asynchronous circuits against a Petri net specification. The technique is based on symbolic reachability analysis, modeling both the specification and the gate-level network behavior by means of boolean functions. These functions are efficiently handled by using Binary Decision Diagrams. Algorithms for verifying the correctness of designs, as well as several circuit properties are proposed. Finally, the applicability of our verification method has been proven by checking the correctness of different benchmarks.

Symbolic analysis of bounded Petri nets

This paper presents a symbolic approach for the analysis of bounded Petri nets. The structure and behavior of the Petri net is symbolically modeled by using Boolean functions, thus reducing reasoning about Petri nets to Boolean calculation. The set of reachable markings is calculated by symbolically firing the transitions in the Petri net. Highly concurrent systems suffer from the state explosion problem produced by an exponential increase of the number of reachable states. This state explosion is handled by using Binary Decision Diagrams (BDDs) which are capable of representing large sets of markings with small data structures. Petri nets have the ability to model a large variety of systems and the flexibility to describe causality, concurrency, and conditional relations. The manipulation of vast state spaces generated by Petri nets enables the efficient analysis of a wide range of problems, e.g., deadlock freeness, liveness, and concurrency. A number of examples are presented in order to show how large reachability sets can be generated, represented, and analyzed with moderate BDD sizes. By using this symbolic framework, properties requiring an exhaustive analysis of the reachability graph can be efficiently verified.

Checking signal transition graph implementability by symbolic BDD traversal

This paper defines conditions for a Signal Transition Graph to be implemented by an asynchronous circuit. A hierarchy of the implementability classes is presented. Our main concern is the implementability of the specification under the restricted input-output interface between the design and the environment, i.e., when no additional interface signals are allowed to be added to the design. We develop algorithms and present experimental results of using BDD-traversal for checking STG implementability. These results demonstrate efficiency of the symbolic approach and show a way of improving existing tools for STG-based asynchronous circuit design.<<ETX>>

Checking delay-insensitivity: 10/sup 4/ gates and beyond

Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verifying circuits whose behavior is independent of component delays (delay-insensitive). It shows that for a particular way of implementing a delay-insensitive circuit, through a Null Convention Logic methodology, the complexity of the verification task might be significantly reduced. This method is implemented using Satisfiability (SAT) solvers and is successfully tested on realistic design examples having tens of thousands of gates.

Structural methods for the synthesis of speed-independent circuits

Most existing tools for the synthesis of asynchronous circuits from Signal Transition Graphs (STGs) derive the reachability graph for the calculation of logic equations. This paper presents novel methods exclusively based on the structural analysis of the underlying Petri net. This methodology can be applied to any STG that can be covered by State Machines and, in particular to all live and safe free-choice STGs. Significant improvements with regard to existing structural methods are provided. The new techniques have been implemented in an experimental tool that has been able to synthesize specifications with over 10/sup 27/ markings, some of them being non-free choice.

Automatic generation of synchronous test patterns for asynchronous circuits

This paper presents a novel approach for automatic test patterngeneration of asynchronous circuits. The techniques used for thispurpose assume that the circuit can only be exercised by applyingsynchronous test vectors, as is done by real-life testers.The main contribution of the paper is the abstraction of thecircuits behavior as a synchronous finite state machine in such away that similar techniques to those currently used for synchronouscircuits can be safely applied for testing.Currently, the fault model being used is the input stuck-at model.Experimental results on different benchmarks show that our approachgenerates test vectors with high fault coverage.

Hierarchical gate-level verification of speed-independent circuits

This paper presents a method for the verification of speed-independent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on the number of state signals (C elements, RS flip-flops) of the circuit. Despite the reduction to complex gates, verification is kept exact. The specification of the environment only requires to describe the transitions of the input/output signals of the circuit and is allowed to express choice and non-determinism. Experimental results obtained from circuits with more than 500 gates show that the computational cost can be drastically reduced when using hierarchical verification.

Review of general and Toeplitz vector bidiagonal solvers

Abstract A comprehensive review of methods for the solution of general and Toeplitz bidiagonal systems of equations on vector computers is performed in this paper. The methods analyzed here are the R -Cyclic Reduction and the Divide and Conquer families of algorithms. For the case of strictly diagonal dominant systems, the early termination of R -Cyclic Reduction and Divide and Conquer algorithms is studied. Also, the Overlapped Partitions Method is analyzed. The methods studied here are tuned for vector processors with different techniques that are explained and analyzed. In particular, one vector processor of the Convex C-3480 is used as a case study and final conclusions for vector and parallel computers are given.

A generalized vision of some parallel bidiagonal systems solvers

In this paper, a review of methods for the solution of general bidiagonal systems of equations is done. Gaussian Elimination, the r-Cyclic Reduction family of algorithms and the Divide and Conquer algorithm are analyzed. A unified view of the three types of methods is proposed. The work is focussed on two basic aspects of the methods: parallelism and grain. The influence of the architecture of the target computer on the parallelism and grain of the methods is evaluated. In particular, vector processors are analyzed as target architecture and one vector processor of the Convex C-3480 is taken as a case study. For the special case of Divide and Conquer, a model is made in order to tune parallelism and grain for its optimal execution. Two conclusions can be outlined from the analysis of the methods. First, the execution time of the r-Cyclic Reduction family of algorithms is lower as r grows reaching a lower significative bound in r=9. This means that the classic use of Cyclic Reduction on vector computers is outdated from now on. Second, the higher rank versions of the r-Cyclic Reduction family of algorithms and the optimized version of Divide and Conquer behave similarly on vector computers.