Erez Ravid

AWV: high-throughput cross-array cross-wafer variation mapping

Minute variations in advanced VLSI manufacturing processes are well known to significantly impact device performance and die yield. These variations drive the need for increased measurement sampling with a minimal impact on Fab productivity. Traditional discrete measurements such as CDSEM or OCD, provide, statistical information for process control and monitoring. Typically these measurements require a relatively long time and cover only a fraction of the wafer area. Across array across wafer variation mapping ( AWV) suggests a new approach for high throughput, full wafer process variation monitoring, using a DUV bright-field inspection tool. With this technique we present a full wafer scanning, visualizing the variation trends within a single die and across the wafer. The underlying principle of the AWV inspection method is to measure variations in the reflected light from periodic structures, under optimized illumination and collection conditions. Structural changes in the periodic array induce variations in the reflected light. This information is collected and analyzed in real time. In this paper we present AWV concept, measurements and simulation results. Experiments were performed using a DUV bright-field inspection tool (UVision(TM), Applied Materials) on a memory short loop experiment (SLE), Focus Exposure Matrix (FEM) and normal wafers. AWV and CDSEM results are presented to reflect CD variations within a memory array and across wafers.

Novel approach for immersion lithography defectivity control to increase productivity

Increase of Depth of Focus (DOF) and higher Numerical Aperture (NA), make of immersion lithography a sub-50nm technology node enabler. At the same time it introduces a range of new defect types, also known as immersion defects. According to the ITRS roadmap, the Smallest Defect Of Interest (SDOI) for the 45nm node has a size of 30nm [1] which is the minimal defect size which poses risk to the integrity of the post litho chain processes. A novel approach of Immersion Defectivity Baseline creation and monitoring has been developed for the 45nm technology node by ASML, supported by Applied Materials. An Immersion Defectivity Baseline consists of: a qualified stack, a dedicated defectivity reticle, a Defect Inspection Tool with an optimized inspection recipe, a Defect Review SEM with an optimized defect review recipe and a defect qualification scheme. The new approach to Immersion Defectivity Baseline creation is based on the combined capabilities of highest resolution bright-field inspection and SEM (Scanning Electron Microscopy) review that are available today, with a unique qualification methodology using printed programmed defects that cover the full printable size range. The inspection tools SDOI detection sensitivity has been optimized for engineering, production as well as monitoring modes, with negligible nuisance rate and basic classification capability followed by highly accurate SEM review and classification. As a result, it enables a stringently controlled, highly efficient, automated defect classification for baseline monitoring and increased productivity. The SEM material analysis sub-apparatus complete the control loop for baseline creation and excursion control. This paper presents a protocol for Immersion Defectivity Baseline creation and control methodologies used for the latest ASML immersion scanner.

Monitoring of lithography modules using defect density inspection systems

The aim of this paper is to present two process monitor methods concerning the early detection of process problems resulting from different components of a lithography module (so-called cluster) under conditions of deep ultraviolet lithography. The lithography clusters are monitored with bare silicon wafers which run through a normal process sequence of the cluster. Then, measurements of critical dimension and defect density are performed. The first measurement indicates whether the focus or the exposure dose run out of their target values, the latter detects defects on, within or underneath the resist which may indicate a process problem in one of the cluster parts. Since defect density measurement inspects all dies on the wafer, it was able to detect process problems that result in massive variations of pattern size when the measured values of critical dimensions were still within their specifications. This helped us to derive instructions for operators and stepper and track maintenance personnel that specify a maximum delay time between exposure and development.