Shimon Levi

Material contrast based inline metrology: process verification and control using back scattered electron imaging on CD-SEM

The Critical Dimension Scanning Electron Microscope (CDSEM) is the traditional workhorse solution for inline process control. Measurements are extracted from top-down images based on secondary electron collection while scanning the specimen. Secondary electrons holding majority of detection yield. These images provide more on the structural information of the specimen surface and less in terms of material contrast. In some cases there is too much structural information in the image which can irritate the measurement, in other cases small but important differences between various material compounds cannot be detected as images are limited by contrast information and resolution of primary scanning beam. Furthermore, accuracy in secondary electron based metrology is limited by charging. To gather the exact required information for certain material compound as needed, a technique, known from material analytic SEM´s has been introduced for inline CDSEM analysis and process control: Low Loss Back Scattered Electron Imaging (LL-BSE). The key at LL-BSE imaging is the collection of only the back scattered electrons (BSE) from outermost specimen surface which undergo the least amount possible of energy loss in the process of image generation following impact of the material by a primary beam. In LL-BSE very good and measurable material distinction and sensitivity, even for very low density material compounds can be achieved. This paper presents new methods for faster process development cycle, at reduced cost, based on LL-BSE mass data mining instead of sending wafers for destructive material analysis.

Buckling characterization of gate all around silicon nanowires

Imaging of suspended silicon nanonwires (SiNW) by SEM reveals that some of the SiNW are buckled. Buckling can impact device performance and it is therefore important to characterize this phenomenon. Measuring the buckling of suspended silicon nanowires (SiNW) poses significant challenges: (1) Small dimensions - SiNW are made with diameters ranging from about 3 to 10 nm and the buckling is of a similar scale. (2) Accurate height measurements – buckling is a three dimensional phenomena. To meet these challenges a new height map reconstruction technique was introduced, using the CDSEM side detectors signal. Measuring pixel by pixel position in X, Y and Z (height) dimensions, we can obtain the buckling vector gradient along the wire in three dimensions. In this paper we present: (1) A description of the height map reconstruction technique used. (2) Three dimensional characterization of SiNW: (a) SiNW buckling measurements (b) Characterization of buckling as a function of the SiNW length and width.

Line edge roughness frequency analysis for SAQP process

The line edge roughness (LER) and line width roughness (LWR) transfer in a self-aligned quadruple patterning (SAQP) process is shown for the first time. Three LER characterization methods, including conventional standard deviation method, power spectral density (PSD) method and frequency domain 3-sigma method, are used in the analysis. The wiggling is also quantitatively characterized for each SAQP step with a wiggling factor. This work will benefit both process optimization and process monitoring.

Edge roughness characterization of advanced patterning processes using power spectral density analysis (PSD)

Self-Aligned Quadruple Patterning (SAQP) is targeted to support the sub 10nm technology nodes. It is consisted of several process steps starting with lithography and Etch to define the pattern backbone. Followed by additional set of processes based on thin-films deposition and etch that quadruple the number of patterns, shrinking pattern and pitch sizes. Pattern roughness is derived from the physical and chemical characteristics of these process steps. It is changing with each of the SAQP process steps, based on material stack and the etch process characteristics. Relative to a sub 10 nm pattern sizes pattern, edge roughness can significantly impact pattern physical dimensions. Unless controlled it can increase the variability of device electrical performance, and reduce yield. In this paper we present the SAQP process steps and roughness characterization, performed with Power Spectral Density (PSD) methodology. Experimental results demonstrates the ability of PSD analysis to sensitively reflect detailed characterization of process roughness, guiding process development improvements, and enabling roughness monitoring for production.

CDSEM AFM hybrid metrology for the characterization of gate-all-around silicon nano wires

In an ongoing study of the physical characterization of Gate-All-Around Silicon Nano Wires (GAASiNW), we found that the thin, suspended wires are prone to buckling as a function of their length and diameter. This buckling takes place between the fixed source and drain regions of the suspended wire, and can affect the device performance and therefore must be studied and controlled. For cylindrical SiNW, theory predicts that buckling has no directional preference. However, 3D CDSEM measurement results indicated that cylindrical wires prefer to buckle towards the wafer. To validate these results and to determine if the electron beam or charging is affecting our observations, we used 3D-AFM measurements to evaluate the buckling. To assure that the CDSEM and 3D-AFM measure the exact same locations, we developed a design based recipe generation approach to match the 3D-AFM and CDSEM coordinate systems. Measuring the exact same sites enables us to compare results and use 3D-AFM data to optimize CDSEM models. In this paper we will present a hybrid metrology approach to the characterization of GAASiNW for sub-nanometer variations, validating experimental results, and proposing methods to improve metrology capabilities.

SEM simulation for 2D and 3D inspection metrology and defect review

Advanced SEM simulation has become a key element in the ability of SEM inspection, metrology and defect review to meet the challenges of advanced technologies. It grants additional capabilities to the end user, such as 3D height measurements, accurate virtual metrology, and supports Design Based Metrology to bridge the gap between design layout and SEM image. In this paper we present SEM simulations capabilities, which take into consideration all parts of the SEM physical and electronic path, interaction between Electron beam and material, multi perspective SEM imaging and shadowing derived from proximity effects caused by the interaction of the Secondary Electrons signal with neighboring pattern edges. Optimizing trade-off between simulation accuracy, calibration procedures and computational complexity, the simulation is running in real-time with minimum impact on throughput. Experiment results demonstrate Height measurement capacities, and CAD based simulated pattern is compared with SEM image to evaluate simulated pattern fidelity.

AWV: high-throughput cross-array cross-wafer variation mapping

Minute variations in advanced VLSI manufacturing processes are well known to significantly impact device performance and die yield. These variations drive the need for increased measurement sampling with a minimal impact on Fab productivity. Traditional discrete measurements such as CDSEM or OCD, provide, statistical information for process control and monitoring. Typically these measurements require a relatively long time and cover only a fraction of the wafer area. Across array across wafer variation mapping ( AWV) suggests a new approach for high throughput, full wafer process variation monitoring, using a DUV bright-field inspection tool. With this technique we present a full wafer scanning, visualizing the variation trends within a single die and across the wafer. The underlying principle of the AWV inspection method is to measure variations in the reflected light from periodic structures, under optimized illumination and collection conditions. Structural changes in the periodic array induce variations in the reflected light. This information is collected and analyzed in real time. In this paper we present AWV concept, measurements and simulation results. Experiments were performed using a DUV bright-field inspection tool (UVision(TM), Applied Materials) on a memory short loop experiment (SLE), Focus Exposure Matrix (FEM) and normal wafers. AWV and CDSEM results are presented to reflect CD variations within a memory array and across wafers.

A holistic metrology sensitivity study for pattern roughness quantification on EUV patterned device structures with mask design induced roughness

Monitoring of pattern roughness for advanced technology nodes is crucial as this roughness can adversely affect device yield and degrade device performance. The main industry work horse for in-line roughness measurements is the CD-SEM, however, today no adequate reference metrology tools exist that allow to evaluate its roughness measurement sensitivity and precision. To bridge this gap, in this work the roughness measurement capabilities of different analytical techniques are investigated. Different metrology methods are used to evaluate roughness on a same set of samples and results are compared and used in a holistic approach to better characterize and quantify the measured pattern roughness. To facilitate the correlation between the various metrology techniques and the evaluation of CD-SEM sensitivity, an effective approach is to induce pattern roughness in a controlled way by adding well defined levels of roughness to the designed patterns on a EUV mask and to measure the response and sensitivity of CD-SEM and of the other techniques to these different pattern roughness levels once printed on wafers. This paper presents the roughness measurement results obtained with various metrology technologies including CD-SEM, OCD, S-TEM and XCD on EUV Lithography patterned wafers both postlithography and post-etch. The benefits of recently developed metrology enhancements are demonstrated as well; automated TEM allows to generate accurate and rather precise reference roughness data, Machine Learning enables OCD based roughness metrology with good correlation to CD-SEM and STEM, and the improved sensitivity of EUV and X-ray scattering systems allows to extract roughness information that does correlate to CD-SEM.

DSA process characterization using BSE metrology (Conference Presentation)

Incorporated in relevant design of guiding templates, DSA (Direct Self Assembly) patterning offers a cost-effective manufacturing method to support pattern shrink for advanced technology nodes. The physical characteristics of the BCP moieties and the self-assembly process, pose unique 3D metrology challenges. Pattern fidelity issues of DSA caused by dislocations, forms residual later that can impact pattern fidelity after Etch. Addressing this challenge can assist the R&D groups to monitor material and process quality to meet patterning specifications. In this paper, we highlight the usage of BSE (Back Scattered Electron) metrology as an innovative approach to characterize the DSA process. Experimental data demonstrate the possibility to characterize the polymer residual layer quality and even assess its thickness for the pattern etch transfer. The quality of the information brought by the BSE imaging make it a must-have to quantify the bottom opening for processed of DSA techniques of pitch multiplication and shrink, from which are not visible with conventional SEM images.

3D SEM characterization of advanced sidewall patterning process (Conference Presentation)

Sidewall image transfer has become a key enabler of future design shrink. It is consisted of several process steps that multiply the number of lithography backbone patterns in a self-aligned form, shrinking pattern and pitch sizes. The quality of the image transfer process depends on the characteristics of the sidewall pattern morphology. Rectangular Sidewalls with a flat top and vertical edges will result with symmetrical and uniform etched image. On the other hand, Facet top, bent sidewalls, sloped edges or foot, may distort the etched image. In this paper we present a description of the 3DSEM metrology technique used, simulation results, and demonstrate three dimensional characterization of Sidewalls pattern fabricated with different etch recipes: o Top Facet measurements vs cross section images o Edge slop and foot characterization