O. Vendier

Thin-film inverted MSM photodetectors

To improve the external quantum efficiency and maintain the high speed of metal-semiconductor-metal (MSM) photodetectors, a thin film inverted MSM (I-MSM), which is separated from the growth substrate, has fingers on the bottom of the device, and is bonded to a silicon host substrate, is reported for the first time. This device optimizes the tradeoff between speed and responsivity, demonstrating the improvement in responsivity that can be achieved using an I-MSM. The photodetector time domain response at /spl lambda/=1.3 /spl mu/m is 50 ps FWHM, with a 34 ps rise time and a 85 ps fall time.

SIMPil: an OE integrated SIMD architecture for focal plane processing applications

Focal plane processing applications present a growing computing need for portable telecomputing and videoputing systems. This paper demonstrates the integration of digital processing, analog interface circuitry, and thin film OE devices into a compact computing package. The SIMPil architecture provides a programmable, silicon efficient SIMD processor for effective execution of early image processing applications such as edge detection, convolution, and compression. Results from a demonstration SIMPil node are presented including its microarchitecture, and performance on image processing applications.

Thin-film multimaterial optoelectronic integrated circuits

The multimaterial integration of thin-film optoelectronic devices with host substrates ranging from silicon circuits to glass waveguides to polymer micromachines offers to the system designer the freedom to choose the optimal materials for each component to achieve performance and cost objectives. Thin-film compound semiconductor optoelectronic devices are comparable to, and, in some cases, better than, their on-wafer counterparts. Thin-film detectors have been integrated with receiver circuits and movable micromachines, thin-film emitters with drive circuitry, and both have been used to demonstrate three-dimensionally interconnected systems. Vertical electrical integration of detector arrays on top of circuits is examined for massively parallel processing of images. Vertical optical interconnections of stacked silicon circuits (which are transparent to the wavelength of light used) are explored, and are used to develop a massively parallel processing architecture based upon low memory, high throughput, and high input/output.

Stacked silicon CMOS circuits with a 40-Mb/s through-silicon optical interconnect

Optical interconnection through stacked silicon foundry complementary metal-oxide-semiconductor (CMOS) circuitry has been demonstrated at a data rate of over 40 Mb/s with an open eye diagram. The system consists of a 0.8-/spl mu/m transmitter and receiver realized in foundry digital CMOS. The use of digital CMOS enables on-chip integration with more complex digital systems, such as a microprocessor. Two layers of these circuits were integrated with thin-film InP-based light emitting diodes and metal-semiconductor-metal photodetectors operating at 1.3 /spl mu/m (to which the silicon is transparent) to enable vertical optical through-Si-communication between the stacked silicon circuits.

A 155 Mbps digital transmitter using GaAs thin film LEDs bonded to silicon driver circuits

A low cost, low power digital silicon transmitter integrated with a GaAs-based surface LED has been fabricated and characterized. Operation at 155 Mbps has been demonstrated with a digital input, resulting in a transmitter which is integrable with digital Si CMOS circuitry, and is suitable for short haul optical communication.

A three-layer 3D silicon system using through-Si vertical optical interconnections and Si CMOS hybrid building blocks

We present for the first time a three-dimensional (3D) Si CMOS interconnection system consisting of three layers of optically interconnected hybrid integrated Si CMOS transceivers. The transceivers were fabricated using 0.8-/spl mu/m digital Si CMOS foundry circuits and were integrated with long wavelength InP-based emitters and detectors for through-Si vertical optical interconnections. The optical transmitter operated with a digital input and optical output with operation speeds up to 155 Mb/s. The optical receiver operated with an external optical input and a digital output up to 155 Mb/s. The transceivers were stacked to form 3D through-Si vertical optical interconnections and a fabricated three layer stack demonstrated optical interconnections between the three layers with operational speed of 1 Mb/s and bit-error rate of 10/sup -9/.

A 100 Mbps, LED Through-Wafer Optoelectronic Link for Multicomputer Interconnection Networks

Through-wafer optoelectronic interconnect offers some architectural alternatives that are not available with wire-based interconnects. In order to compete with wire-based technologies, optoelectronic interconnects must provide reasonable performance in terms of bandwidth, bit error rate (BER), and power, using inexpensive and manufacturable devices. This paper presents a 100 Mbps link design under development as part of a scalable three-dimensional multicomputer network for a 4096 node system. Empirical and analytical data for emitters, detectors, receivers, and optical coupling is used to examine the tradeoffs between link power and bit error rate (BER). Because multicomputer networks demand extremely low BERs (10?15?10?20),hop-by-hoperror correction circuitry is incorporated to optimize BER, providing a robust channel. This approach employs a novel adaptation of the widely used wormhole routing protocol to minimize overhead and maximize compatibility with existing interconnect techniques.

Design issues for through-wafer optoelectronic multicomputer interconnects

The paper presents several design issues associated with the implementation of a three dimensional optically interconnected parallel processing system. A technique for improving bit error rate in low power multistage networks is presented. Error detection codes are transmitted along with message data to guarantee the integrity of the data during each optical hop. To realize three dimensional through silicon wafer interconnect, thin film emitters and detectors operating at a wavelength of 1.3 /spl mu/m (to which silicon is transparent) will be bonded to the silicon circuitry. A transfer diaphragm process is used to realize this integration; this process has been used to demonstrate the basic concept: a single silicon circuit has been integrated with both a thin film emitter and detector operating at 1.3 /spl mu/m wavelength (K.H. Calhoun et al., 1993). We utilize one possible integration scenario to illustrate the trade offs associated with a system of this type, which includes device design, circuit design, and issues which include manufacturability, alignment tolerance, crosstalk, and power dissipation.

Scaleable CMOS Current-Mode Preamplifier Design for anOptical Receiver

We have designed a process-insensitive preamplifierfor an optical receiver, fabricated it in several different minimumfeature sizes of standard digital CMOS, and demonstrated designscaleability of this analog integrated circuit design. The sameamplifier was fabricated in a 1.2 µm and two different0.8 µm processes through the MOSIS foundry [1].The amplifier uses a multi-stage, low-gain-per-stage approach.It has a total of 5 identical cascaded stages. Each stage isessentially a current mirror with a current gain of 3. Threeof these preamplifiers have been integrated with a GaAs Metal-Semiconductor-Metal (MSM) photodetector and one with anInGaAs MSM detector by using a thin-film epilayer device separationand bonding technology [2]. This quasi-monolithic front-end of anoptical receiver virtually eliminates the parasitics between thephotodetector and the silicon CMOS preamplifier. We have demonstratedspeed and power dissipation improvement as the minimum feature sizeof the transistors shrink.

3D stacked Si CMOS VLSI smart pixels using through-Si optoelectronic interconnections

We have presented the first demonstration of an optically interconnected three dimensional smart pixel system connecting three stacked layers of Si CMOS VLSI circuitry. We have demonstrated vertical optical communication between three CMOS circuit layers with operation speeds up to 1 Mbps. This system demonstrates the viability of implementing optical interconnections for scalable 3D interconnection systems for ultra-smart pixel applications.