Eric D. Marsman

Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache

Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-pad memories lack the complex tag checking and comparison logic, thereby proving to be efficient in area and power. In this work, we focus on exploiting scratch-pad memories for storing hot code segments within an application. Static placement techniques focus on placing the most frequently executed portions of programs into the scratch-pad. However, static schemes are inherently limited by not allowing the contents of the scratch-pad memory to change at run time. In a large fraction of applications, the instruction memory footprints exceed the scratch-pad memory size, thereby limiting the usefulness of the scratch-pad. We propose a compiler managed dynamic placement algorithm, wherein multiple hot code sequences, or traces, are overlapped with each other in the scratch-pad memory at different points in time during execution. Special copy instructions are provided to copy the traces into the scratch-pad memory at run-time. Using a power estimate, the compiler initially selects the most frequent traces in an application for relocation into the scratch-pad memory. Through iterative code motion and redundancy elimination, copy instructions are inserted in infrequently executed regions of the code. For a 64-byte code cache, the compiler managed dynamic placement achieves an average of 64% energy improvement over the static solution in a low-power embedded microcontroller.

A 0.5-to-480MHz Self-Referenced CMOS Clock Generator with 90ppm Total Frequency Error and Spread-Spectrum Capability

This work demonstrates a self-referenced CMOS LCO, or CMOS harmonic oscillator (CHO), that exhibits 90ppm total frequency error over process, bias and temperature, thus making it suitable for replacing XOs in many applications. Additionally, the clock generator can be configured to produce a number of different output frequencies, has 1/4 of the frequency error of the oscillator in [3] and includes a direct modulation technique enabling SSCG.

A Top-Down Microsystems Design Methodology and Associated Challenges

An overview of microsystems technology is presented along with a discussion of the recent trends and challenges associated with its development. A typical bottom-up design methodology is described and we propose, in contrast, an efficient and effective top-down methodology. We illustrate its implementation with the development of a microsystem design that has been completed and fabricated in CMOS technology. Gaps in the tool capabilities are identified and suggestions for future directions in CAD tool support for microsystems technology are presented.

A 25-MHz Self-Referenced Solid-State Frequency Source Suitable for XO-Replacement

Recent trends in the development of integrated silicon frequency sources are discussed. Within that context, a 25-MHz self-referenced solid-state frequency source is presented and demonstrated where measured performance makes it suitable for replacement of crystal oscillators (XOs) in data interface applications. The frequency source is referenced to a frequency-trimmed and temperature-compensated 800-MHz free-running LC oscillator (LCO) that is implemented in a standard logic CMOS process and with no specialized analog process options. Mechanisms giving rise to frequency drift in integrated LCOs are discussed and supported by analytical expressions. Design objectives and a compensation technique are presented where several implementation challenges are uncovered. Fabricated in a 0.25-mum 1P5M CMOS process, and with no external components, the prototype frequency source dissipates 59.4 mW while maintaining plusmn152 ppm frequency inaccuracy over process, plusmn 10% variation in the power supply voltage, and from - 10degC to 80degC. Variation against other environmental factors is also presented. Nominal period jitter and power-on start-up latency are 2.75 psrms and 268 mus, respectively. These performance metrics are compared with an XO at the same frequency.

A silicon die as a frequency source

A monolithic and unpackaged silicon die is presented as a frequency source suitable for quartz crystal resonator (XTAL) and oscillator (XO) replacement. The frequency source is referenced to a free-running, frequency-trimmed and temperature-compensated 3GHz RF LC oscillator. A programmable divider array enables the device to provide frequencies ranging from 6 to 133MHz. A post-processed Faraday shield contains fringing electromagnetic fields and enables the device to be delivered in unpackaged form such that it can be assembled into any package or via any assembly technique. The device dissipates approximately 2mA from a 1.8–3.3V power supply and drifts no more than ±300ppm over all operating conditions including a panel of industry-standard reliability tests.

Partitioning variables across register windows to reduce spill code in a low-power processor

Low-power embedded processors utilize compact instruction encodings to achieve small code size. Such encodings place tight restrictions on the number of bits available to encode operand specifiers and, thus, on the number of architected registers. As a result, performance and power are often sacrificed as the burden of operand supply is shifted from the register file to the memory due to the limited number of registers. In this paper, we investigate the use of a windowed register file to address this problem by providing more registers than allowed in the encoding. The registers are organized as a set of identical register windows where, at each point in the execution, there is a single active window. Special window management instructions are used to change the active window and to transfer values between windows. This design gives the appearance of a large register file without compromising the instruction encoding. To support the windowed register file, we designed and implemented a graph partitioning-based compiler algorithm that partitions program variables and temporaries referenced within a procedure across multiple windows. On a 16-bit embedded processor, an average of 11 percent improvement in application performance and 25 percent reduction in system power was achieved as an 8-register design was scaled from one to two windows.

A 16-bit low-power microcontroller with monolithic MEMS-LC clocking

Low-power, single-chip integrated systems are prevailing in remote applications due to the increasing power and delay cost of inter-chip communication compared to on-chip computation. The paper describes the design and measured performance of a fully-functional digital core with a low-jitter, monolithic, MEMS-LC clock reference. This chip has been fabricated in TSMCs 0.18 μm MM/RF bulk CMOS process. Maximum power consumption of the complete microsystem is 48.78 mW operating at 90 MHz with a 1.8 V power supply.

Increasing the number of effective registers in a low-power processor using a windowed register file

Low-power embedded processors utilize compact instruction encodings to achieve small code size. Instruction sizes of 8 to 16 bits are common. Such encodings place tight restrictions on the number of bits available to encode operand specifiers, and thus on the number of architected registers. The central problem with this approach is that performance and power are often sacrificed as the burden of operand supply is shifted from the register file to the memory due to the limited number of registers. In this paper, we investigate the use of a windowed register file to address this problem by providing more registers than allowed in the encoding. The registers are organized as a set of identical register windows where at each point in the execution there is a single active window. Special window management instructions are used to change the active window and to transfer values between windows. The goal of this design is to give the appearance of a large register file without compromising the instruction encoding. To support the windowed register file, we designed and implemented a novel graph partitioning based compiler algorithm that partitions virtual registers within a given procedure across multiple windows. On a 16-bit embedded processor with a parameterized register window, an average of 10% improvement in application performance and 7% reduction in system power was achieved as an eight-register design was scaled from one to four windows.

Performance analysis using pipeline visualization

High-end microprocessors are increasing in complexity to push the limits of speed and performance. As a result, analyzing these complex system can be an arduous task. Architectural simulators, acting as sofrware processors, are able to run programs and give statistics about the performance of the code on the design. While these statistics are valuable for identifying problems, they often do not provide the fidelity necessary to diagnose the cause of sluggish performance. This paper presents a cross-platform tool that can be used to visualize the flow of instructions through an architectural processor pipeline model. The Graphical Pipeline Viewel; GPC: uses a colorized pipeline trace display to deliver an efJicient diagnostic and analysis environment. The resource view of the tool, which can display cycle statistics, aids in distinguishing possible bottlenecks and architectural trade-ogs. As such, the tool is able to suggest code and architectural modifications to increase program performance.’

DSP architecture for cochlear implants

This paper describes low-power DSP architecture for use in cochlear implants. The microsystem, fabricated in TSMC 0.18mum CMOS, consumes 1.79mW from a 1.2V supply and occupies an area of 9.18mm2 while providing the necessary programmability for high speech comprehension by patients. Standby power consumption is 330muW