Sundus Kubba

A Monolithic and Self-Referenced RF LC Clock Generator Compliant With USB 2.0

A monolithic and self-referenced radio frequency (RF) LC clock generator that is compliant with USB 2.0 is demonstrated in a system-on-chip (SoC). This work presents the first successful approach to replacing an external crystal (XTAL), the crystal oscillator (XO) and the phase-locked loop for clock generation in an IC supporting USB 2.0 using a standard CMOS fabrication process. It is shown that the primary design challenges with the implemented approach involve maintaining high frequency accuracy and low jitter. Techniques for addressing both are shown. In particular, the presented architecture exploits the effects of frequency division and low far-from-carrier phase noise to achieve low jitter. From a 1.536 GHz temperature-compensated LC reference oscillator, coherent clock signals are derived at 96MHz for the SoC logic and 12 MHz for an on-chip full-speed USB PHY. Though self-referenced, approximately plusmn400ppm total frequency accuracy is achieved over process variations, plusmn10% variation in the USB power supply voltage and temperature variation from -10 to +85degC. Measured period and cycle-to-cycle jitter are 6.78 psrms and 8.96 psrms, respectively. Fabricated in a 0.35 mum CMOS technology, the clock generator occupies 0.22 mm2 and draws 9.5 mA from a 3.3-V supply, which is derived from the 5-V USB power supply

A 0.5-to-480MHz Self-Referenced CMOS Clock Generator with 90ppm Total Frequency Error and Spread-Spectrum Capability

This work demonstrates a self-referenced CMOS LCO, or CMOS harmonic oscillator (CHO), that exhibits 90ppm total frequency error over process, bias and temperature, thus making it suitable for replacing XOs in many applications. Additionally, the clock generator can be configured to produce a number of different output frequencies, has 1/4 of the frequency error of the oscillator in [3] and includes a direct modulation technique enabling SSCG.

A 25-MHz Self-Referenced Solid-State Frequency Source Suitable for XO-Replacement

Recent trends in the development of integrated silicon frequency sources are discussed. Within that context, a 25-MHz self-referenced solid-state frequency source is presented and demonstrated where measured performance makes it suitable for replacement of crystal oscillators (XOs) in data interface applications. The frequency source is referenced to a frequency-trimmed and temperature-compensated 800-MHz free-running LC oscillator (LCO) that is implemented in a standard logic CMOS process and with no specialized analog process options. Mechanisms giving rise to frequency drift in integrated LCOs are discussed and supported by analytical expressions. Design objectives and a compensation technique are presented where several implementation challenges are uncovered. Fabricated in a 0.25-mum 1P5M CMOS process, and with no external components, the prototype frequency source dissipates 59.4 mW while maintaining plusmn152 ppm frequency inaccuracy over process, plusmn 10% variation in the power supply voltage, and from - 10degC to 80degC. Variation against other environmental factors is also presented. Nominal period jitter and power-on start-up latency are 2.75 psrms and 268 mus, respectively. These performance metrics are compared with an XO at the same frequency.

DSP architecture for cochlear implants

This paper describes low-power DSP architecture for use in cochlear implants. The microsystem, fabricated in TSMC 0.18mum CMOS, consumes 1.79mW from a 1.2V supply and occupies an area of 9.18mm2 while providing the necessary programmability for high speech comprehension by patients. Standby power consumption is 330muW

Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking

A low-latency, HDL-synthesizable dynamic clock frequency controller is presented as a time-efficient alternative to full-custom implementations. Frequency division of a fully integrated hybrid temperature-compensated LC oscillator (TC-LCO) and ring oscillator clock reference avoids PLL locking delays to enable low-latency, hazard-free frequency selection on an actively running CPU. Fabricated in 0.18mum CMOS as part of a low-power SoC microsystem, the circuit dissipates 480muW at 1.8V

A 9.2mW 528/66/50MHz monolithic clock synthesizer for mobile /spl mu/P platforms

A low-power monolithic clock synthesizer suitable for use in mobile /spl mu/P platforms is presented. Clock synthesis is accomplished using an all-Si RF LC reference oscillator that does not require an external frequency reference. Fabricated in 0.18/spl mu/m CMOS, the developed clock synthesizer demonstrates /spl plusmn/1% frequency accuracy over process, voltage, and 0-70/spl deg/C, exhibits 7.4/21/33ps/sub rms/ period jitter on 528/66/50MHz clock signals, and achieves a start-up latency of only 3.2/spl mu/s.

A 25MHz all-CMOS reference clock generator for XO-replacement in serial wire interfaces

A 25 MHz all-CMOS clock generator is demonstrated where measured performance makes it suitable for direct replacement of the reference crystal oscillator (XO) for serial wire interfaces. Fabricated in a 0.25 mum 1P5M logic CMOS process, and with no external components, the developed clock generator dissipates 59.4 mW while exhibiting plusmn152 ppm frequency error over process, plusmn10% variation in the power supply voltage and from -5-75degC. Nominal period jitter and power-on start-up latency are 3.93 psrms and 268 mus respectively.