Eric Lindbloom

Transition Fault Simulation

Delay fault testing is becoming more important as VLSI chips become more complex. Components that are fragments of functions, such as those in gate-array designs, need a general model of a delay fault and a feasible method of generating test patterns and simulating the fault. The authors present such a model, called a transition fault, which when used with parallel-pattern, single-fault propagation, is an efficient way to simulate delay faults. The authors describe results from 10 benchmark designs and discuss add-ons to a stuck fault simulator to enable transition fault simulation. Their experiments show that delay fault simulation can be done of random patterns in less than 10% more time than needed for a stuck fault simulation.

Failure diagnosis of structured VLSI

The authors describe a method for diagnosing the failures observed in testing VLSI designs that use the scan-path structure. Diagnosis consists of simulating selected faults after testing using a fault simulator that allows the application of several patterns in parallel. The method is also suitable for signature-based random-pattern testing. The authors discuss diagnostic fault simulation, fault-list generation, relating faults to defects, diagnostic strategy, and random-pattern failures, and they report some experimental results to indicate the procedures power.<<ETX>>

Random-pattern coverage enhancement and diagnosis for LSSD logic self-test

Embedded linear feedback shift registers can be used for logic component self-test. The issue of test coverage is addressed by circuit modification, where necessary, of random-pattern-resistant fault nodes. Also given is a procedure that supports net-level diagnosis for structured logic in the presence of random test-pattern generation and signature analysis.

A method for generating weighted random test pattern

A new method for generating weighted random patterns for testing LSSD logic chips and modules is described. Advantages in using weighted random versus either deterministic or random test patterns are discussed. An algorithm for calculating an initial set of input-weighting factors and a procedure for obtaining complete stuck-fault coverage are presented.

Fault detection effectiveness of weighted random patterns

Performance results are given for use of a weighted random pattern test generator, WRP, on ten benchmark designs. Deterministic (DET) and WRP tests created for single stuck faults are compared in their ability to detect shorts and transition faults. The WRP is able to generate a test for all the single stuck faults detected with a state-of-the-art deterministic pattern generator; WRP is highly efficient in CPU time required for full stuck fault test pattern generation; both DET and WRP achieved high net-to-net shorts fault coverage on a sample of ten designs; and WRP had significantly higher ( approximately=11%) transition fault coverage than obtained with DET for the same sample.<<ETX>>

A heuristic test-pattern generator for programmable logic arrays

This paper describes a heuristic method for generating test patterns for Programmable Logic Arrays (PLAs). Exploiting the regular structure of PLAs, both random and deterministic test-pattern generation techniques are combined to achieve coverage of crosspoint defects. Patterns to select or deselect product terms are generated through direct inspection of an array; test paths to an observable output are established by successive, rapidly converging assignmemnts of primary input values. Results obtained with a PL/I program implementation of the method are described; these results demonstrate that the method developed is both effective and computationally inexpensive.