Donato O. Forlenza

Application and analysis of IDDQ diagnostic software

A current disadvantage of IDDq testing is lack of software-based diagnostic tools that enable IC vendors to create a large database of defects uniquely detected with this test method. We present a methodology for performing defect localization based upon IDDq test information (only). Using this technique, fault localization can be completed within minutes (e.g. <5 minutes) after IC testing is complete. This technique supports multiple fault models and has been successfully applied to a large number of samples-including ones that have been verified through failure analysis. Data is presented related to key issues such as diagnostic resolution, hardware-to-fault model correlation, diagnostic current thresholds, and the diagnosability of various defect types.

On-chip power supply noise measurement using Time Resolved Emission (TRE) waveforms of Light Emission from Off-State Leakage Current (LEOSLC)

In this paper, a new emission-based method for measuring the amplitude of on-chip power supply noise is presented. This technique uses Time Resolved Emission (TRE) waveforms of Light Emission from Off-State Leakage Current (LEOSLC) from CMOS gates, which are used as local probe points for the noise. In order to demonstrate the capabilities of this technique, we discuss the results obtained for two early microprocessor chips fabricated in 65 nm and 45 nm Silicon On Insulator (SOI) technologies.

Structural and functional test of IBM system z10 chips

For the first time in the history of the IBM System z™ family of mainframes, System z10™ processor chips are tested by both structural and functional means. This complementary strategy starts at wafer test and is consistent through system test. In this paper, we describe how traditional and enhanced structured patterns provide fault coverage and how functional patterns mimic real system workloads. A new operating kernel generates functional tests and expected results and it can run these tests for either a finite or an indefinite amount of time to simulate system operation. It also executes custom hand-loop patterns to stress chip temperature and power. Both structural and functional patterns are used to uniquely characterize each chip. Adaptive algorithms based on results at wafer test determine optimal system operating voltage for each chip--a strategy that delivers a chip supply with optimal characteristics for system manufacturing and product delivery. The diversity of structural and functional patterns makes it possible to increase z10™ chip quality and reduce development time. The ability to run the same tests from wafer through system test provides a consistency not previously possible.

Testing the IBM Power 7™ 4 GHz eight core microprocessor

The IBM Power 7™ 4 GHz, eight core microprocessor introduced several new challenges for the Power 7 test team: new pervasive test architecture, 8 asynchronous processor cores, DRAM integrated on the same die as processor and enhanced thermal test requirements. The design complexity, time to market schedule compression, and rapid production ramp required innovation and new methods to meet these challenges. The following is an overview of the design for test architecture, manufacturing test methodology, thermal calibration, and rapid yield learning deployed to address these challenges and deliver a leadership server processor.

Weighted random test program generation for a per-pin tester

The authors present an overview of a comprehensive software system that serves as an automatic bridge between computer-aided-design- (CAD-) generated weighted random patterns (WRPs-) and a per-pin tester that incorporates dedicated hardware to support WRP testing. A test program generation system that integrates a level-sensitive-scan-design (LSSD-) based design system with a per-pin tester containing WRP hardware has been architected. This system generates complete test programs and permits the direct release of hundreds of ASIC (application-specific integrated circuit) devices into manufacturing. The benefits of low test data volume, improved test coverage, and finer diagnostic resolution provided by the WRP methodology are realized. The capture of delay defects is aided by the availability of several timing edges on a per-pin basis.<<ETX>>