Eric M. Foster

Design of an MPEG-2 transport demultiplexor core

A new high-performance MPEG-2 transport demultiplexor hardware architecture is presented which minimizes the support required from a host processor for common tasks such as clock recovery and table section filtering, yet provides an interface for a processor to modify the handling of the incoming transport stream. A common on- chip SRAM is used for temporary storage of transport packets as they are processed, as well as for control and status registers, allowing space for efficient storage and reducing silicon size. Memory storage is further reduced by delivering data directly to the audio and video decoder rate buffers and to system memory as part of a total, integrated MPEG subsystem design. The architecture is implemented as part of the IBM Blue Logic™ core library.

ESD packaging requirements for an opto-electronic receiver module

Sensitive circuits contained in an optoelectronic receiver module must meet worldwide standards for electrostatic discharge (ESD). Enclosing these circuits in a package becomes an extremely important consideration in achieving acceptable module performance. The authors describe the packaging requirements for an optoelectronic module that will meet the objective. Experimental tests were conducted on various packaging designs to determine the significant features affecting ESD susceptibility. Areas investigated included metallurgical vs. metal-filled epoxy assembly of the package elements (housing, lid, substrate), and low resistance vs. full closure between the packaging elements. The packaging features required to achieve acceptable ESD voltage levels were determined and implemented in the design. >

The Electrical Effect of Single-Chip CMOS Packages

It is becoming increasingly important to understand the electrical effects of packaging before being committed to expensive hardware. Unfortunately, complex and time-consuming computer simulation is necessary to predict accurately the electrical performance of a package system. While this type of analysis must be done during the final stage of the development cycle to ensure an adequate design, a simpler technique is needed in the conceptualization stage. Several generic package designs have been characterized and inserted into two comprehensive simulation models that were operated at various CMOS switching speeds. The results of this detailed study are summarized in a series of charts that correlate relative packaging system noise to both module design and to device speed. In referring to these graphs, the electrical performance of one packaging approach with respect to another can be approximated. This information can be used during the trade-off studies associated with the early phase of development to determine the effect of various design alternatives.

Integrating the MPEG-2 subsystem for digital television

An MPEG-2 subsystem consisting of the transport demultiplexor, audio decoder, and video decoder is described, along with the supporting processor and memory subsystem. This subsystem is directly applicable to set-top box designs used in a digital television broadcast environment. The advantages of an integrated MPEG-2 subsystem consisting of cores from the IBM Blue Logic library are discussed. The integrated architecture supports a shared memory address space implemented using the PowerPC® local bus (PLB) standard high-speed bus. The resulting memory-management improvements for on-screen display (OSD), decoder rate buffers, audio and video clip data, and transport system data are illustrated. The real-time memory bandwidth and latency requirements for processing an MPEG-2 stream also have an impact on the architecture of the subsystem. Additional enhancements are provided for channel changes, time-base changes, error handling, and enhanced processing in the transport by adding more specialized buses. Programming effort is reduced because the software has less responsibility managing data movement through the system and because the same programming method is used to control all of the MPEG-2 functions.

High-performance packaging of gigabit data communication optical modules

Packaging technology is described for the DM-1062 gigabit optical module. This module is the IBM offering to comply with ANSI XT39.3 Fiber Channel Standard (FCS) for 1.0625 Gb/s optoelectronic transceiver with integrated serializer/deserializer functions. Performance data for this module is discussed as well as extensions of this technology to lower cost optical devices.