Richard Eugene Anderson

Design of an MPEG-2 transport demultiplexor core

A new high-performance MPEG-2 transport demultiplexor hardware architecture is presented which minimizes the support required from a host processor for common tasks such as clock recovery and table section filtering, yet provides an interface for a processor to modify the handling of the incoming transport stream. A common on- chip SRAM is used for temporary storage of transport packets as they are processed, as well as for control and status registers, allowing space for efficient storage and reducing silicon size. Memory storage is further reduced by delivering data directly to the audio and video decoder rate buffers and to system memory as part of a total, integrated MPEG subsystem design. The architecture is implemented as part of the IBM Blue Logic™ core library.

Integrating the MPEG-2 subsystem for digital television

An MPEG-2 subsystem consisting of the transport demultiplexor, audio decoder, and video decoder is described, along with the supporting processor and memory subsystem. This subsystem is directly applicable to set-top box designs used in a digital television broadcast environment. The advantages of an integrated MPEG-2 subsystem consisting of cores from the IBM Blue Logic library are discussed. The integrated architecture supports a shared memory address space implemented using the PowerPC® local bus (PLB) standard high-speed bus. The resulting memory-management improvements for on-screen display (OSD), decoder rate buffers, audio and video clip data, and transport system data are illustrated. The real-time memory bandwidth and latency requirements for processing an MPEG-2 stream also have an impact on the architecture of the subsystem. Additional enhancements are provided for channel changes, time-base changes, error handling, and enhanced processing in the transport by adding more specialized buses. Programming effort is reduced because the software has less responsibility managing data movement through the system and because the same programming method is used to control all of the MPEG-2 functions.

Common Mode Return Loss Consideration in Wirebond Packaging for High Speed SerDes Links

This paper discusses the trade-offs in performance and cost of high speed SerDes in wirebond package applications. While many protocol standards specify requirements for both common mode return loss and differential mode return loss, meeting both sets of requirements in low cost wirebond packages requires the designer to make significant trade-offs. The performance and cost impacts of improving common mode return loss in wirebond packaging is examined from several different points of view