Eric W. Strid

LRM and LRRM Calibrations with Automatic Determination of Load Inductance

Two new techniques are presented in an effort to achieve greater accuracy and better repeatability in the on-wafer calibration of vector network analyzers. The first is a method of determining an inductance value for the match standard during the calibration process so that only its resistance, not its reactance, needs to be known. The second is a new type of calibration, LRRM (line-reflect-reflect-match), which is a variation of LRM with several possible advantages. Also, a simple series resistance-inductance model for a coplanar load is experimentally investigated to 40 GHz and found to provide a good description of the load behavior.

Evaluation of TSV and micro-bump probing for wide I/O testing

Practical silicon stacking requires pre-tested dies, but contact probing of TSV interconnects requires much higher density, lower probing forces, and lower cost per pin than conventional probe cards have achieved. This paper examines a cost-effective, lithographic-based MEMS probe card technology that is suitable for probing 40µm pitch arrays, and scalable to finer pitches. Initial mechanical and electrical results are presented, demonstrating the feasibility of probing large arrays at 1 gram-force per tip with very low pad damage, so as not to impair downstream bonding or other processing steps.

Surface-Mounted GaAs Active Splitter and Attenuator MMIC's Used in a 1-10-GHz Leveling Loop

A wide-band monolithic GaAs bridge-T variable attenuator has been used with a monolithic GaAs active power splitter to form a compact 1-10-GHz leveling loop having a minimum 9-dB leveling range with buffered output. The attenuator internally optimizes input and output return loss over a 1-10-GHz bandwidth by the use of on-chip GaAs op-amp. The active power splitter provides unity gain to each port over a 1-10-GHz bandwidth by the use of distributed amplification. The entire 4.5-cm by 4.2-cm subsystem was realized with surface mount packages on RT-Duroid®, demonstrating new construction techniques for GaAs MMIC assembly.

Where Are My On-Wafer Reference Planes?

In order to characterize the accuracy of on-wafer measurements, there is the need to understand microwave waver probe calibrations over a matrix of planar transmission line types, sizes, and substrate materials. One of the calibration issues which arise is the electrical lengths of the planar calibration standards relative to each other and relative to the device under test. In this paper, three techniques for verifition of planar calibration standards are presented and shown to agree within ±0.1 ps of electrical length.

A probe technology for 110+ ghz integrated circuits with aluminum pads

There is a growing interest in probing Si-based RFICs and test structures with aluminum pads. Probing RFICs with aluminum pads is significantly more difficult than probing ICs with gold pads. This is because a thin layer of aluminum oxide (about 60 angstroms thick) naturally forms on the aluminum surface that impairs the electrical contact between the tips of the probes and the aluminum pads. Any measurement that is sensitive to a series resistance will be affected by contact resistance variations. Such measurements include inductor Q measurements and long characterization tests that require repeatable device contact for time periods beyond a few minutes (Schreurs, 2001). Conventional probes use tungsten tips to penetrate the aluminum oxide layer. Unfortunately, the tungsten itself also oxidizes and the aluminum oxide, after only a few contacts, accumulates on the tips of the probes, significantly increasing the contact resistance and hence resulting in measurement deterioration (Kister, 1998). As a remedy, frequent cleaning of the probe tips is obligatory. Worse, the operator is usually unsure of the precision of the measurements, due to the non-repeatable nature of the contact resistance. Recently probe card developments based on polyimide membrane technology showed superior performance on aluminum pads (Smith, 1999). In this paper, and based on this technology, we present a new single-port RF probe for aluminum pads that has a superior performance compared to conventional probes

Accurate measurement of high-speed package and interconnect parasitics

The feasibility of using high-speed wafer probes to measure accurately the parasitics associated with packages and interconnects used in conjunction with high-speed integrated circuits is demonstrated. A way of calibrating out the fixture-related errors while providing a reconfigurable mechanical interface to specific points of interest is demonstrated. These points can be at the perimeter and also internal. Calibration at the point of interface to the structure under test and a well-controlled mechanical interface enable large numbers of highly repeatable measurements to be made easily and accurately. The effect is to extend the full capability of test instrumentation to the physical points of interest, with accuracy and repeatability from site to site. The ability to calibrate at the probe tips is necessary to eliminate distortions from cables and probes. Some sources of errors, such as crosstalk, should be minimized in the probe, since they are difficult to correct in most cases.<<ETX>>

Impedance Matching Probes for Wireless Applications

This work describes the motivation, technology, design, and performance of impedance matching probes that address the needs of wireless applications. The impedance matching solution can be implemented in two distinctly different technologies, air-coplanar and thin-film membrane. Impedance matched probes offer improved load-pull characterization of power, gain and efficiency, and accurate characterization of devices with non-standard impedances.

Chapter 2 Electronic Wafer Probing Techniques

Publisher Summary This chapter discusses electronic wafer probing techniques, high-speed sampling oscilloscopes, and frequency–domain characterization methods. The major advantage of high-speed real-time oscilloscopes is in the display of nonrecurrent waveforms. Oscilloscopes operating in continuous mode usually employ a travelling-wave structure cathode-ray tube, where the vertical deflection signal travels with the same velocity as the deflected electron beam. While real-time oscilloscopes with less than 100 ps resolution have been reported, sampling methods are much more common in this speed range. The chapter distinguishes between equivalent-time sampling oscilloscopes, which need recurrent coherent signals to operate, and real-time sampling oscilloscopes, which do not have these restraints. Theoretically, a real-time sampling oscilloscope multiplies the input signal with a periodic stream of impulses to yield an output function, which contains the amplitude of the sampled signal at discrete times. Equivalent-time sampling oscilloscopes may employ two different methods for performing the sampling process. In sequential-sampling oscilloscopes, the delay increases monotonically with every occurrence of the input waveform.

Optimized impedance standard substrate designs for dual and differential applications

Optimized dual signal Impedance Standard Substrate (ISS) designs are demonstrated. The optimal designs had loop-under grounds, were selected for minimum deviation from lumped element behavior and used mode dampening structures. A comparison of existing design approaches is given and the quality of the designs is illustrated to 50 GHz.

High-Throughput RFIC Wafer Testing

This paper surveys the state of RFIC wafer testing as performed on production floors today, and the trends and expectations for the future. Currently, most RF chips sold as known-good die (KGD) and relatively complex RFICs are tested at-speed at the wafer level. RF wafer testing is used to reduce the cost of scrap at the next level of packaging, and various test strategies are pursued to reduce test costs. The hardware options and tradeoffs for production testing are surveyed. Finally, the outlook for test cost, ATE resources, chip connection density, and for emerging technologies such as built-in self-test, are discussed.