Jonathan Saul

Logic synthesis for arithmetic circuits using the Reed-Muller representation

A procedure for multi-level Reed-Muller minimization has been developed which introduces a Reed-Muller factored form, and uses algebraic algorithms for factorization, decomposition, resubstitution, collapsing, and extraction of common cubes and subexpressions. The procedure has been used to design some arithmetic circuits using a gate library containing a wide range of gates, and the resulting circuits were compared with some designed using MisII. The circuits designed using the Reed-Muller system were over 20 percent smaller and between 25 and 50 percent faster.<<ETX>>

An improved algorithm for the minimization of mixed polarity Reed-Muller representations

The use of the Reed-Muller representation to represent and manipulate switching functions in logic synthesis systems is discussed. An algorithm for the minimization of mixed-polarity Reed-Muller representations to multiple-output incompletely specified switching functions is presented, in which heuristics are used to determine the best application of previously known rules for minimizing single-output equations; rules are used to link multiple-output functions and to minimize incompletely specified functions. This algorithm has been implemented, and benchmark comparisons with the best previous minimization method known shows that the method is faster and results in smaller representations.<<ETX>>

An algorithm for the multi-level minimization of Reed-Muller representations

There is interest currently in using Reed-Muller equations as a way of representing and manipulating switching functions, and as a means of designing circuits based on exclusive-OR gates. There are only two-level Reed-Muller minimizers in use, although the need for a multi-level minimizer has been identified. A procedure for multi-level Reed-Muller minimization has been developed. It introduces a Reed-Muller factored form and uses algebraic algorithms for factorization decomposition, resubstitution, collapsing, and extraction of common cubes and sub-expressions. The procedure has been implemented in C as a series of packages which have been added to MISII, and benchmark comparisons with minimal two-level representations are favorable.<<ETX>>

DART: delay and routability driven technology mapping for LUT based FPGAs

A two-phased approach for routability directed delay-optimal mapping of LUT based FPGAs is presented based on the results of stochastic routability analysis. First, delay-optimal mapping is performed which simultaneously minimizes area and delay. Then, the mapped circuits are restructured to alleviate the potential routing congestions. Experimental results indicate that the first phase creates designs which require 17% fewer levels and 40% fewer LUTs than MIS-pga (delay), 11% fewer levels and 37% fewer LUTs than FlowMap-r, and 5% fewer levels and 39% fewer LUTs than TechMap-D. The success of the second phase is confirmed by running a vendors layout tool APR. It is observed that they are more routable and have less final delays than those produced by other mappers if they are placed and routed.

State assignment algorithms for parallel controller synthesis

Algorithms for parallel controller synthesis that operate on a matrix representation of the controller are presented. This matrix is first simplified and then used to generate a state assignment with which the controller can be synthesized. Results show that a parallel controller often yields significant improvements in circuit area and speed, compared to its functionally equivalent finite-state machine.<<ETX>>

Architecture oriented logic optimization for lookup table based FPGAs

A logic optimization criterion for lookup-table based field programmable gate arrays (FPGAs) is presented. Based on this criterion, several key operations of logic optimization, such as extraction, decomposition, resubstitution and simplification, are discussed, so as to make them evaluate the circuit cost in accordance with the target technology. Using our approaches to do logic optimization for lookup-table based FPGAs, we obtain a good starting point for technology mapping. On the basis of 25 benchmark examples, our optimized circuits require 14% fewer configurable logic blocks (CLBs) than the circuits optimized by MIS-II if both are subsequently mapped using MIS-pga. Moreover, the number of circuit levels is also slightly improved.<<ETX>>

Behavioral synthesis of complex parallel controllers

A CAD system for automatic behavioural synthesis of synchronous parallel controllers from their Petri net specifications is presented. The system operates on an unfolded Petri nets model of a controller which is called an occurrence net. Having the net unfolded, a set of sequential components of the Petri net is identified, and a state assignment is performed with which the controller can be synthesized. The experimental results show that the method presented in this paper is significantly faster then previous methods.

Technology mapping of mixed polarity Reed-Muller representations

There is interest in using Reed-Muller forms (exclusive-OR sums of products) as a representation in logic synthesis. There are algorithms available for two-level and multilevel minimization, but there is a lack of techniques for sum of products technology mapping. Two methods are presented: a simple rule-based method which decomposes the representations until they match a gate in the library; and a more sophisticated directed acyclic graph (DAG) mapping method which covers a directed acyclic graph representation of the network with DAG representations of gates from the gate library. Both methods have been implemented, and full sets of results are given. A number of suggestions are made for improving both methods.<<ETX>>