Ernesto Martins

Combining operational flexibility and dependability in FTT-CAN

The traditional approaches to the design of distributed safety-critical systems, due to fault-tolerance reasons, have mostly considered static cyclic table-based traffic scheduling. However, there is a growing demand for operational flexibility and integration, mainly to improve efficiency in the use of system resources, with the network playing a central role to support such properties. This calls for dynamic online traffic scheduling techniques so that dynamic communication requirements are adequately supported. Nevertheless, using dynamic traffic management mechanisms raises additional problems, in terms of fault-tolerance, related with the weaker knowledge of the future system state caused by the higher level of operational flexibility. Such problems have been recently addressed in the scope of using flexible time-triggered CAN (FTT-CAN) in safety-critical applications in order to benefit from the high operational flexibility of this protocol. This paper gathers and reviews the main mechanisms that were developed to provide dependability to the protocol, namely, master replication and fail-silence enforcement.

Architecture of a fieldbus message scheduler coprocessor based on the planning paradigm

Abstract The use of a centralised planning scheduler in fieldbus-based systems requiring real-time operation has proved to be a good compromise between operational flexibility and timeliness guarantees. It is particularly well adapted to embedded systems based on low-processing power microcontrollers due to the low overhead it imposes. In this paper a preliminary implementation of a hardware scheduling coprocessor based on the planning paradigm is presented. The coprocessor is installed in a special node of the fieldbus, the bus arbiter, and generates scheduling tables to be dispatched by the node CPU. With this solution it is possible to decrease the response time to changes in the system configuration or message parameters of the software-based planning scheduler. This opens the possibility of allowing automatic on-line changes requested by system nodes in addition to the ones requested by human operators, thus improving system reactivity. The paper includes a short review of the planning technique and a discussion on the motivation to develop the coprocessor as well as on recent similar and related work. The coprocessor architecture and several implementation details such as its interface with the arbiter CPU are presented. The initial calculations showing the feasibility of the unit are also derived, together with the first real implementation of the coprocessor itself.

Components to Enforce Fail-Silent Behavior in Dynamic Master-Slave Systems

Abstract This paper considers the case in which master-slave fieldbus networks are used in safety-critical embedded applications, such as transportation systems. Traditional approaches to system design, due to fault-tolerance reasons, have considered static cyclic table-based traffic scheduling, only. However, there is a growing demand for flexibility and integration, mainly to improve efficiency in the use of system resources, with the network playing a central role to support such properties. This calls for dynamic on-line traffic scheduling techniques so that dynamic communication requirements are adequately supported. This paper considers such dynamic master-slave architectures and addresses the problem of enforcing fail silent behavior both in the master and in the slave nodes. Two different mechanisms are proposed, one based on dynamic bus guardians for the slave nodes only, to impose fail silent behavior in the time domain, and other based on internal replication and temporized agreement, to impose fail silence both in the temporal and value domains. Despite being potentially applicable to a set of master-slave networks, this paper discusses the specific implementation of the proposed mechanisms on top of the FTT-CAN protocol.

A low-noise CMOS front-end for TOF-PET

An analogue CMOS front-end for triggering and amplification of signals produced by a silicon photomultiplier (SiPM) coupled to a LYSO scintillator is proposed. The solution is intended for time-of-flight measurement in compact Positron Emission Tomography (TOF-PET) medical imaging equipments where excellent timing resolution is required ( ≈ 100ps). A CMOS 0.13μm technology was used to implement such front end, and the design includes preamplification, shaping, baseline holder and biasing circuitry, for a total silicon area of 500x90 μm. Waveform sampling and time-over-threshold (ToT) techniques are under study and the front-end provides fast and shaped outputs for time and energy measurements. Post layout simulation results show that, for the trigger of a single photoelectron, the time jitter due to the pre-amplifier noise can be as low as 15 ps (FWHM), for a photodetector with a total capacitance of 70 pF. The very low input impedance of the pre-amplifier ( ≈ 5Ω) allows 1.8 ns of peaking time, at the cost of 10 mW of power consumption.

Frequency characterization of memristive devices

This paper proposes a new methodology suitable for frequency characterization of memristive devices (MDs) and systems. MDs are usually described by their associated hysteresis loops. Their distinctive memory properties stem from this unusual characteristic. Understanding the frequency behavior of these devices is of paramount importance for a multitude of different applications. This paper presents a morphological method, based on loop area and the length for the analysis of the frequency dependence of MDs. An example, considering thin film TiO2 MDs reveals that the limit frequency (frequency where the loop has maximum area) of the device depends strongly on device dimensions and physical properties.

An FPGA-based coprocessor for real-time fieldbus traffic scheduling: architecture and implementation

Distributed computer control systems used nowadays in the industry need often to meet requirements of on-line reconfigurability so they can adjust dynamically to changes in the application environment or to evolving specifications. The communication network connecting the computer nodes, commonly a fieldbus system, must use therefore dynamic scheduling strategies, together with on-line admission control procedures that test the validity of all changes in order to guarantee the satisfaction of real-time constraints. These are both very computationally demanding tasks, something that has precluded their wide adoption. However, these algorithms also embed sufficient levels of parallelism to grant them benefits from implementations in dedicated hardware.This paper presents a scheduling coprocessor that executes dynamic real-time traffic scheduling and schedulability analysis. The FPGA-based implementation described here supports multiple scheduling policies and was tailored for the FTT-CAN protocol, but it can be used also in other fieldbuses relying on centralized scheduling. The coprocessor generates schedules in about two orders of magnitude less time than any practical network elementary cycle duration. The time to execute a schedulability test is deterministic. An evaluation based on the SAE benchmark yielded a worst-case execution time of 1.4 ms.The paper starts by discussing the scheduling problem being addressed. It describes then the coprocessor functionality and architecture, highlighting important design decisions, and its latest implementation. Finally the coprocessor performance evaluation is presented.

Amplitude characterization of memristive devices

Memristive Devices (MDs) are usually described by their associated hysteresis loops. Their distinctive memory properties stem from this unusual characteristic, which depends on both stimulus frequency and amplitude. Understanding the behavior of these devices is of paramount importance for a multitude of different applications. This paper investigates the dependency of loop area and length on stimulus amplitude of MDs. The characterization methodology follows the morphological approach, introduced by the authors in [10], for frequency characterization. An example, considering thin film TiO2 MDs reveals that the peak amplitude (amplitude where the loop has maximum area) of the device depends strongly on device dimensions and physical properties.

Traffic scheduling coprocessor with schedulability analysis capability

The low processing power of typical fieldbus nodes used in real-time applications usually limits the sort of message scheduling that can be done, and precludes any kind of on-line schedulability analysis. Moving these computationally intensive tasks to dedicated hardware is an effective way to remove this limitation and achieve the best temporal determinism. This paper presents a traffic scheduling and schedulability analyser coprocessor targeted for centralised scheduling fieldbus systems. The FPGA-based coprocessor generates message schedules according to one of three different scheduling policies, and allows the number of message and their respective parameters to be change dynamically. The schedulability analyser capability supports on-line admission control of new messages. The paper starts by discussing the basic feature which such a coprocessor should include. Then the coprocessor architecture is described together with several relevant implementation details. Finally the worst case execution times of its two main functions are derived, validating the coprocessors feasibility.

Design of an OS9 operating system extension for a message-passing multiprocessor

Abstract This paper describes an interprocess communication system built around a message-passing model which we have developed for a bus-based multiprocessor. It is based on an OS9 operating system kernel in each processor, and comprises an integrated set of system modules. These manage message communication between processors and provide a global communication interface for application processes through which they can exchange messages in a transparent way. The implementation uses channels and virtual circuits and the communication primitives support synchronous and asynchronous message transfer, and group communication.

An operating system extension for a multiprocessor

Abstract In the last few years computer architectures based on multiple processors have massively crossed the border from the mere academic research systems domain to the real world of industrial and consumer applications. New operating systems (OSs) for these parallel machines are now readily available. Some are true multiprocessor or distributed OSs, others are simpler single processor multitasking OSs which have been extended to allow users to take advantage from parallel machines with a minimum cost. In this paper we present a practical development based on this last approach – an extension for the Microwares OS9 operating system which we have developed for our bus-based multiprocessor. The OS extension adds basically a new interprocess communication (IPC) mechanism, which is built around the message model using channels and virtual circuits. Application processes residing on different processors communicate through messages in a transparent way. The IPC performance figures obtained match or exceed the ones reported for similar systems. The presentation highlights the problems faced and the solutions found in the implementation of well-known OS concepts.