Ernisse S. Putna

Demonstration of full-field patterning of 32 nm test chips using EUVL

EUV lithography is considered one of the options for high volume manufacturing (HVM) of 16 nm MPU node devices [1]. The benefits of high k1(~0.5) imaging enable EUVL to simplify the patterning process and ease design rule restrictions. However, EUVL with its unique imaging process - reflective optics and masks, vacuum operation, and lack of pellicle, has several challenges to overcome before being qualified for production. Thus, it is important to demonstrate the capability to integrate EUVL into existing process flows and characterize issues which could hamper yield. A patterning demonstration of Intels 32 nm test chips using the ADT at IMEC [7] is presented, This test chip was manufactured using processes initially developed with the Intel MET [2-4] as well as masks made by Intels mask shop [5,6]. The 32 nm node test chips which had a pitch of 112.5 nm at the trench layer, were patterned on the ADT which resulted in a large k1 factor of 1 and consequently, the trench process window was iso-focal with MEEF = 1. It was found that all mask defects detected by a mask pattern inspection tool printed on the wafer and that 90% of these originated from the substrate. We concluded that improvements are needed in mask defects, photospeed of the resist, overlay, and tool throughput of the tool to get better results to enable us to ultimately examine yield.

Printability of extreme ultraviolet lithography mask pattern defects for 22-40 nm half-pitch features

Assessing the printability of EUV (extreme ultraviolet) lithography mask pattern defects is critical for determining EUV mask patterning, defect metrology, and repair technology requirements. Printability of mask defects at the wafer level depends on defect size, defect shape, defect location, and the line width and pitch of the structure being printed. Earlier reports showed the relationship between the defect size on the mask and the printed critical dimension for 40-70 nm dense lines. Improvements in the EUVL process now enable assessment of mask pattern defect printability for 22-40 nm half-pitch features. We report here the smallest mask pattern defects that printed at different locations in 22-40 nm structures using the Intel Micro-Exposure Tool (MET). Various types of defects such as indentations or protrusions were purposely incorporated into features on an EUV mask. The sizes of the patterned defects on the mask were drawn between 10-250 nm (= 2-50 nm on the wafer). The minimum printable defect size varied by over 100 nm, depending on the defect shape and location.