Ertugrul Demircan

Integration of SiCN as a low /spl kappa/ etch stop and Cu passivation in a high performance Cu/low /spl kappa/ interconnect

This paper describes the integration of a silicon carbon nitride (SiCN) copper passivation and etch stop layer into a Cu low k dielectric interconnect technology. The incorporation of SiCN improves interconnect performance by virtue of its lower dielectric constant as compared to silicon nitride, and through changes to the process integration made possible by the improved etch selectivity and good copper interface properties.

Effects of Interconnect Process Variations on Signal Integrity

With the development of new sub micron very large scale integration (VLSI) technologies the importance of interconnect parasitics on delay and noise has been in an ever increasing trend [1]. Consequently, the variations in interconnect parameters have a larger impact on final timing and functional yield of the product. Therefore, it is necessary to handle process variations as accurately as possible in layout parasitic extraction (LPE), static timing (ST) and signal integrity (SI) in deep sub-micron designs. In this paper we analyze the sources of process variation that induce interconnect parasitic variations. We present the relatively important ones through the usage of a response surface model (RSM). It was found that, in addition to metal thickness and width variation, damaged dielectric regions on the side of the metal lines are important contributions to cross-talk. We demonstrate the importance of accounting for the correlation between parameters for a given interconnect line such as interconnect line resistance and thickness. Finally we present a Monte Carlo (MC) methodology based on the RSM which can significantly reduce separation of corners and lead to tighter product specs and hence smaller die area and lower power.

Model based method for electro-migration stress determination in interconnects

Electro-migration (EM) failure in interconnects is one of the most important reliability considerations in current advanced semiconductor technologies. As the technology features are pushed to the limit and with the introduction of new materials and increased current densities to satisfy the performance demands, the EM failure risk is ever-increasing. In this paper we present a novel methodology based on a model-based approach where EM risk can be assessed for any interconnect geometry through an exact solution of the fundamental stress equations. This approach eliminates the need for complex look-up tables for different geometries and can be implemented in CAD tools very easily.