Mehul D. Shroff

Realistic Projections of Product Fails from NBTI and TDDB

Statistical models for deconvolving the effects of competing mechanisms on product failures are presented. Realistic projections of product fails are demonstrated on high performance microprocessors by quantifying the contribution of NBTI, TDDB and extrinsic fail mechanisms. In particular, it is shown that transistor shifts due to NBTI manifest as population tails in the products minimum operating voltage (Vmin) distribution, while TDDB manifests as single-bit or logic failures that constitute a separate sub-population. NBTI failures are characterized by lognormal statistics combined with a slower degradation rate (Deltat ~ t0.15 -t0.25), in contrast to TDDB failures that follow extreme-value statistics and exhibit a faster degradation rate (DeltaVt ~ t0.5)

A novel biasing technique for addressable parametric arrays

Addressable arrays that use switches to isolate the devices being tested are limited in size and utility by the parasitic leakage caused by those switches. A new biasing technique that reduces the leakage of these switches has been studied to address this problem. Simulations performed in a 90 nm low-power technology predicted almost a two-decade drop in parasitic leakage of the array. Experimental data confirmed this improvement. 1 times 32 and 4 times 32 arrays using this biasing technique were used to investigate probe pad effects, device variability and geometry dependence.

A Novel Biasing Technique for Addressable Parametric Arrays

Addressable arrays that use switches to isolate the devices being tested are limited in size and utility by the parasitic leakage caused by those switches. A new biasing technique that removes the drain-source bias from these switches has been studied to address this problem. Simulations performed in a 90 nm low-power technology predicted more than a two-decade drop in parasitic leakage of the array. Experiment data performed on a 90 nm technology confirmed this improvement.

Terrestrial SER characterization for nanoscale technologies: A comparative study

In this work, the efforts of an industry wide consortium to characterize the logic soft error rate of a multitude of combinational and sequential logic circuits across multiple technologies is reported. The basic intent of the approach was to bring together the designs and intellectual property of various semiconductor companies on a single technology platform to be tested and compared under the same experimental conditions. This ensures that the measured results are validated, comparable and benchmarked against other similar designs. More importantly, crucial findings associated with this collaborative effort are also outlined in this paper. Some of the key results include the fact that scaling has led to the steady decline of failure in time (FIT) rates for flip-flops as well as combinational logic circuits. Additionally, the improvement in the soft error resilience provided by redundant node flip-flops has reduced with technology miniaturization due to the effects of charge sharing and multiple node charge collection. In spite of this, however, at high frequencies, the combinational logic soft error rate is comparable to the soft error rate of typical flip-flops. The experimental results are complemented with modeling various soft error mechanisms that affect modern high speed logic circuits.

Model based method for electro-migration stress determination in interconnects

Electro-migration (EM) failure in interconnects is one of the most important reliability considerations in current advanced semiconductor technologies. As the technology features are pushed to the limit and with the introduction of new materials and increased current densities to satisfy the performance demands, the EM failure risk is ever-increasing. In this paper we present a novel methodology based on a model-based approach where EM risk can be assessed for any interconnect geometry through an exact solution of the fundamental stress equations. This approach eliminates the need for complex look-up tables for different geometries and can be implemented in CAD tools very easily.

Test structure to evaluate the impact of neighboring features on stress of metal interconnects

The stress-inducing effects of neighboring metal interconnect features were studied using novel stressmigration test structures with various layouts of perpendicular neighboring combs. The structures with narrow widths showed no change in stressmigration performance, with or without near-neighbor structures. However, structures built with wider lines showed up to 3X worse stressmigration performance when perpendicular combs were present nearby, essentially independent of the spacing to the combs. Thus, near neighbor metal features were shown to be capable of degrading SM performance in some lines.