Esa Petri

Design and Verification of Hardware Building Blocks for High-Speed and Fault-Tolerant In-Vehicle Networks

This paper presents the design, implementation, and validation of a FlexRay transceiver and a SpaceWire (SpW) router and interface, which constitute the main hardware building blocks of the two in-vehicle communication standards. The FlexRay protocol features data rates up to 10 Mb/s and time- and event-triggered transmissions, along with scalable fault-tolerance support, and it is expected to become the standard network for X-by-wire and active safety automotive systems. However, collision avoidance and driver-assistance applications based on camera/radar sensors require data rates up to hundreds of megabits per second as well as fault tolerance, features that can hardly be covered by current or expected automotive standards. In this scenario, a promising technology seems to be the new SpW protocol, currently used in avionics and aerospace.

Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip

Clock distribution is an important issue when designing multi processor systems-on-chip on deep sub-micron technology nodes and non-synchronous approaches are becoming popular in this field. This work presents a low-complexity link microarchitecture for mesochronous on-chip communication that enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. With respect to the state of the art, the proposed link architecture stands for its low power and low complexity overheads; moreover it can be easily integrated in a conventional digital design flow since it is implemented by means of standard cells only. Results are presented referring to the link integrated within a multi processor tiled architecture based on a network-on-chip communication backbone on a CMOS 65 nm technology.

Sensor Modeling, Low-Complexity Fusion Algorithms, and Mixed-Signal IC Prototyping for Gas Measures in Low-Emission Vehicles

This paper addresses the detection of hydrogen leaks for safety warning systems in automotive applications and the measurement of nitrogen oxide concentration in exhaust gases of zero-emission vehicles. The presented approach is based on the development of accurate models (including nonlinearity and error sources of real building components) for all the system elements: sensors and acquisition chain. This methodology enables efficient design space exploration and sensitivity analysis, allowing an optimal analog-digital and hardware-software partitioning. Such analysis drives also the development of effective data fusion techniques to reduce the measure uncertainty (due to cross-sensitivity to other gases or to temperature/humidity variations). Such techniques have been implemented on a microcontroller-based mixed-signal embedded platform for intelligent sensor interfacing with limited complexity, suitable for automotive applications.

Radiation Tolerant SpaceWire Router for Satellite On-Board Networking

The European Space Agency (ESA) recently proposed the space wire standard for reliable satellite on-board networking at high speeds. This paper presents the design of configurable space wire router and interface hardware macrocells, the first in state-of-the-art compliant with the latest standard extensions, protocol identification and remote memory access protocol. The space wire router with 8 links achieves 100 Mbits/s data rate with 135 W power consumption and 300 Krad radiation tolerance. These performances meet the requirements of planned ESA space missions

Design of an NoC Interface Macrocell with Hardware Support of Advanced Networking Functionalities

This paper presents the design and the characterization in nanoscale CMOS technology of a Network Interface (NI) for on-chip communication infrastructure with hardware support of advanced networking functionalities: store & forward (S&F) transmission, error management, power management, ordering handling, security, QoS management, programmability, end-to-end protocol interoperability, remapping. The design has been conceived as a scalable architecture: The advanced features can be added on top of a basic NI core implementing data packetization and conversion of protocols, frequency and data size between the connected Intellectual Property (IP) core and the on chip network. The NI can be configured to reach the desired tradeoff between supported services and circuit complexity.

FPGA-based networking systems for high data-rate and reliable in-vehicle communications

The amount of electronic systems introduced in vehicles is continuously increasing: X-by-wire, complex electronic control systems and above all future applications such as automotive vision and safety warnings require in-car reliable communication backbones with the capability to handle large amount of data at high speeds. To cope with this issue and driven by the experience of aerospace systems, the SpaceWire standard, recently proposed by the European space agency (ESA), can be introduced in the automotive field. The SpaceWire is a serial data link standard which provides safety and redundancy and guarantees to handle data-rates up to hundreds of Mbps. This paper presents the design of configurable SpaceWire router and interface hardware macrocells, the first in state of the art compliant with the newest standard extensions, Protocol Identification (PID) and remote memory access protocol (RMAP). The macrocells have been integrated and tested on antifuse technology in the framework of an ESA project. The achieved performances of a router with 8 links, 130 Mbps data-rate, 1.5 W power cost, meet the requirements of future automotive electronic systems. The proposed networking solution simplifies the connectivity, reducing also the relevant volume and mass budgets, provides network safety and redundancy and guarantees to handle very high bandwidth data flows not covered by current standards as CAN or FlexRay

Hardware Building Blocks for High Data-Rate Fault-Tolerant In-vehicle Networking

This paper discusses the hardware implementation of high speed and fault-tolerant communication systems for in-vehicle networking. Emerging safety-critical automotive control systems, such as X-by-wire and active safety, need complex distributed algorithms. Large bunches of data have to be exchanged in real-time and with high dependability between electronic control units, sensors and actuators. According to this perspective, the FlexRay protocol, which features data-rates up to 10 Mb/s, time and event triggered transmissions, as well as scalable fault-tolerance support, was developed and it is now expected to become the future standard for in-vehicle communication. However, collision avoidance and driver assistance applications based on vision/radar systems, poses requirements on the communication systems that can hardly be covered by current and expected automotive standards. A candidate that will play a significant role in the development of safety systems which need data-rates up to hundreds of Mb/s as well as fault-tolerance seems to be the new SpaceWire protocol, whose effectiveness has already been proved in avionic and aerospace. This paper presents the design of the major hardware building blocks of the FlexRay and SpaceWire protocols.

VLSI design of a digital RFI cancellation scheme for VDSL transceivers

In this paper, a digital RFI (radio frequency interference) canceller for DMT (discrete multitone modulation)-based VDSL (very high-speed digital subscriber line) systems is presented. The adopted algorithm is optimized in terms of performance vs. complexity and size of the involved memories. High level, maximum precision system simulations showed the effectiveness of the cancellation scheme, considering VDSL performance parameters such as bit rate and efficiency in counteracting performance degradation due to RFI. The canceller has been implemented as a hardware macro-cell: the design space already explored at algorithm level to meet a good complexity/performance trade-off, has been deeply investigated during the bit true analysis to fix the finite numeric representation, the micro-architecture definition and the final technology mapping. Results of logic synthesis on a standard cells 0.18 /spl mu/m CMOS technology are reported, in terms of area and energy consumption.

A mesochronous physical link architecture for network-on-chip interconnects

Clock distribution is a major issue when implementing system-on-a-chip in deep sub-micron technologies. This work presents a new mesochronous physical link architecture, named SKIL, which enables full bandwidth communication between macrocells clocked by signals with the same frequency and an arbitrary amount of skew. SKIL is implemented using standard-cells design flows. It introduces two clock cycles of latency and negligible area and leakage power overheads. Implementation results are presented on a 65 nm CMOS technology.

Hardware/Software FPGA-based Network Emulator for High-speed On-board Communications

This paper presents a network emulator for rapid prototyping of SpaceWire Intellectual Property cores. SpaceWire is a fault-tolerant high-throughput standard widely used in space and avionic applications. Thanks to its inherent properties, SpaceWire can be effectively adopted for addressing dependability and bandwidth requirements of forthcoming active safety automotive applications. The proposed platform considers both anti-fuse and SRAM FPGA devices. A four-layer software stack ensures full control of prototype features, batch testing and ease of use.