Pierangelo Terreni

A Digitally Controlled Shunt Capacitor CMOS Delay Line

Delay-controlled CMOS delay lines have been proved useful in a number of applications, notably the digitization of short time intervals. This paper introduces a new kind of CMOS delay line, in which the delay element is an array of capacitors controlled by a digital signal vector. This choice allows for a robust implementation of the circuitry controlling the delay generation, while the maximum speed attainable by the line is high compared to the maximum speed achieved by other delay line architectures. The delay line presented here was designed to produce an accurately tunable 16 × 0.5ns delay under large temperature, supply voltage, and technological process quality variations.

Sensor Modeling, Low-Complexity Fusion Algorithms, and Mixed-Signal IC Prototyping for Gas Measures in Low-Emission Vehicles

This paper addresses the detection of hydrogen leaks for safety warning systems in automotive applications and the measurement of nitrogen oxide concentration in exhaust gases of zero-emission vehicles. The presented approach is based on the development of accurate models (including nonlinearity and error sources of real building components) for all the system elements: sensors and acquisition chain. This methodology enables efficient design space exploration and sensitivity analysis, allowing an optimal analog-digital and hardware-software partitioning. Such analysis drives also the development of effective data fusion techniques to reduce the measure uncertainty (due to cross-sensitivity to other gases or to temperature/humidity variations). Such techniques have been implemented on a microcontroller-based mixed-signal embedded platform for intelligent sensor interfacing with limited complexity, suitable for automotive applications.

Architectural-Level Power Optimization of Microcontroller Cores in Embedded Systems

Power saving is becoming one of the major design drivers in electronic systems embedding microcontroller cores. Known microcontrollers typically save power at the expense of reduced computational capability. With reference to an 8051 core, this paper presents a novel clustered clock gating to increase power efficiency at architectural level without performance loss and preserving the reusability of the macrocell. Different from known clustered-gating strategies where the number of clusters is fixed a priori, the optimal cluster organization is derived, considering both the macrocell complexity and switching activity. When implementing the 8051 core in CMOS technology, the proposed approach leads to a 37% power saving, which is higher than the 29% permitted by automatic-clock-gating insertion in commercial computer-aided design tools or the 10% of state-of-the-art clustered-gating strategies. To assess its full functionality, the power-optimized cell has been proved in silicon that is embedded in an automotive system for sensors interface/control

A Novel Bit-Level Systolic Array Median Filter

This paper presents examples of the application of ethopharmacology to the study of aggression. Low doses of benzodiazepines may increase aggression under appropriate conditions. In various animal models in male and female rats and mice the aggression enhancing effects are particularly marked when aggression is inhibited by internal or external events. It is therefore suggested that benzodiazepines have no direct effect on aggression, but modulate inhibitory factors which regulate aggression.

Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems

This work presents an FFT/IFFT core compiler particularly suited for the VLSI implementation of OFDM communication systems. The tool employs an architecture template based on the pipelined cascade principle. The generated cores support run-time programmable length and transform type selection, enabling seamless integration into multiple mode and multiple standard terminals. A distinctive feature of the tool is its accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results of the generated macrocells are presented for two deep sub-micron standard-cells libraries (65 and 90nm) and commercially available FPGA devices. When compared with other tools for automatic FFT core generation, the proposed environment produces macrocells with lower circuit complexity expressed as gate count and RAM/ROM bits, while keeping the same system level performance in terms of throughput, transform size and numerical accuracy.

A 250-ps time-resolution CMOS multihit time-to-digital converter for nuclear physics experiments

This paper presents a CMOS realization of a time-to-digital converter (TDC) for nuclear physics experiments. An innovative and robust architecture, already used in a previous TDC version with 1 ns of bin size, has been adopted and improved with the aim to achieve a 500-ps bin size. The TDC has eight input channels plus a common channel. It can store up to 32 events per channel with a double-hit resolution of 8 ns. It can realize common-start and common-stop operations. It has 4.2 ms of input range with a 125-MHz system clock. The chip uses an asynchronous interpolator system based on a delay-locked line to increase the coarse resolution. It has been fabricated in a double-metal single poly n-well, 1-/spl mu/m CMOS process with an area of about 77 mm/sup 2/. Measurements show that the TDC has better performance compared to similar devices, especially the time resolution below 250 ps.

Multihit multichannel time-to-digital converter with /spl plusmn/1% differential nonlinearity and near optimal time resolution

An eight-channel, 1 ns bin-size, 23 b dynamic range, single-chip, multihit, time-to-digital converter (TDC) is presented in this paper. A new architecture mixing two previous TDC realizations has been adopted. The chip can execute common-start or common-stop operations on the trailing, leading, or both transitions of the input channels; it stores at least 32 events/channel with a double-hit resolution of 16 ns. A prototype of about 120 mm/sup 2/ has been integrated into a double-metal, single-poly, n-well 1 /spl mu/m CMOS process, and its performance has been compared to that of similar devices. Test results show that a differential nonlinearity error of /spl plusmn/1%, an integral nonlinearity less than 0.2 least significant hit (LSB), and a time resolution of 0.443 LSB-significantly better than those of comparable TDCs and very close to the theoretical limit of 0.408 LSB-have been achieved.

70-MHz 2- mu m CMOS bit-level systolic array median filter

An algorithm for VLSI median filtering of one-dimensional signals of complexity linearly dependent on the filter window length is described. The algorithm is implemented as a bit-level systolic array (BLSA), in order to achieve high performance. A single-chip median filter characterized by a window length of 25 8-b samples, and by operation on three interleaved independent sequences for a total of 75 samples, is presented as a demonstration of the concept. The throughput relevant to one sequence is 1/3 for this chip, whereas the theoretical maximum allowed by the algorithm is 1/2. Prototypes designed with a 2- mu m CMOS technology have been successfully tested at a clock frequency over 70 MHz. >

Efficient Calibration through Statistical Behavioral Modeling of a High-Speed Low-Power ADC

We address the problem of calibrating a flash analog-to-digital converter (ADC) for ultra-wide band energy-constrained receivers. To achieve a superior power efficiency the ADC exploits an unusual comparator architecture that is capable of avoiding the reference ladder, but need threshold calibration for offset compensation. In this work, we present a foreground calibration technique, which aims at reducing the required energy by minimizing the number of clock cycles required for calibration. Optimization is performed relying on a fast and accurate ADC statistical behavioral model, which is also useful to characterize different calibration schemes and provide feedback to the system designer, avoiding expensive electrical simulations. The proposed technique is successfully applied to a 4-bit 90nm CMOS ADC prototype, obtaining INL< 0.15LSB, DNL<0.2LSB and 3.7-ENOB at 1.25GS/s at the expense of only 15.17nJ ADC energy

A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18/spl mu/m CMOS with 5.8GHz ERBW

We present a 4-bit power scalable flash analog-to-digital converter in digital 0.18-μm CMOS, targeting low power ultra-wide band receivers. To minimize static power consumption, we exploit dynamic comparators with built-in digitally tunable thresholds. The converter has been realized and tested outperforming recent comparable designs even in more advanced technologies. The main performance figures include 5.8GHz effective resolution bandwidth and 0.8pJ/conversion-step at 1-GS/s and Nyquist conditions.