Sergio Saponara

Batteries and battery management systems for electric vehicles

The battery is a fundamental component of electric vehicles, which represent a step forward towards sustainable mobility. Lithium chemistry is now acknowledged as the technology of choice for energy storage in electric vehicles. However, several research points are still open. They include the best choice of the cell materials and the development of electronic circuits and algorithms for a more effective battery utilization. This paper initially reviews the most interesting modeling approaches for predicting the battery performance and discusses the demanding requirements and standards that apply to ICs and systems for battery management. Then, a general and flexible architecture for battery management implementation and the main techniques for state-of-charge estimation and charge balancing are reported. Finally, we describe the design and implementation of an innovative BMS, which incorporates an almost fully-integrated active charge equalizer.

Design and Verification of Hardware Building Blocks for High-Speed and Fault-Tolerant In-Vehicle Networks

This paper presents the design, implementation, and validation of a FlexRay transceiver and a SpaceWire (SpW) router and interface, which constitute the main hardware building blocks of the two in-vehicle communication standards. The FlexRay protocol features data rates up to 10 Mb/s and time- and event-triggered transmissions, along with scalable fault-tolerance support, and it is expected to become the standard network for X-by-wire and active safety automotive systems. However, collision avoidance and driver-assistance applications based on camera/radar sensors require data rates up to hundreds of megabits per second as well as fault tolerance, features that can hardly be covered by current or expected automotive standards. In this scenario, a promising technology seems to be the new SpW protocol, currently used in avionics and aerospace.

Dynamic control of motion estimation search parameters for low complex H.264/AVC video coding

This paper presents a novel technique to reduce the motion estimation (ME) complexity in H.264/AVC video coding. A low complexity context-aware controller is added to a basic search engine; at coding time the controller extracts from the search engine partial results information on the input signal statistics, using them to dynamically configure the ME search parameters, such as number of reference frames, valid block modes and search area. Unnecessary computations and memory accesses can be avoided, decreasing ME complexity while keeping unaltered coding efficiency for a wide range of applications: bit-rates from tens of kbits/s to tens of Mbits/s and video formats from QCIF to CCIR. The context-aware control can be used with any ME search engine and in the paper is successfully applied to full search and fast ME, as EPZS and UMHS, in the JM10 software model of H264/AVC

Sensing Devices and Sensor Signal Processing for Remote Monitoring of Vital Signs in CHF Patients

Nowadays, chronic heart failure (CHF) affects an ever-growing segment of population, and it is among the major causes of hospitalization for elderly citizens. The actual out-of-hospital treatment model, based on periodic visits, has a low capability to detect signs of destabilization and leads to a high re-hospitalization rate. To this aim, in this paper, a complete and integrated Information and Communication Technology system is described enabling the CHF patients to daily collect vital signs at home and automatically send them to the Hospital Information System, allowing the physicians to monitor their patients at distance and take timely actions in case of necessity. A minimum set of vital parameters has been identified, consisting of electrocardiogram, SpO2, blood pressure, and weight, measured through a pool of wireless, non-invasive biomedical sensors. A multi-channel front-end IC for cardiac sensor interfacing has been also developed. Sensor data acquisition and signal processing are in charge of an additional device, the home gateway. All signals are processed upon acquisition in order to assert if both punctual values and extracted trends lay in a safety zone established by thresholds. Per-patient personalized thresholds, required measurements and transmission policy are allowed. As proved by first medical tests, the proposed telemedicine platform represents a valid support to early detect the alterations in vital signs that precede the acute syndromes, allowing early home interventions thus reducing the number of subsequent hospitalizations.

Design and Test of an HV-CMOS Intelligent Power Switch With Integrated Protections and Self-Diagnostic for Harsh Automotive Applications

The design and characterization in high-voltage (HV)-CMOS technology of an innovative intelligent power switch (IPS) for harsh automotive applications is proposed in this paper. To safely handle the ordinary and extraordinary automotive electrical and environmental conditions, a systematic design flow is followed: several design solutions are presented at the architectural and circuital level, integrating on-chip self-diagnostic capabilities and full protection against the high voltage and reverse polarity, the effects of wiring parasitics, and the over-current and over-temperature phenomena. Moreover, the current slope and soft start integrated techniques ensure a low electromagnetic interference, and the IPS is also configurable to efficiently drive different interchangeable loads. The innovative IPS has been implemented in a 0.35-μm HV-CMOS technology and has been embedded in mechatronic third generation brush-holder regulator system-on-chip for an automotive alternator. The electrical simulations and experimental characterization and the testing at component and on-board system levels prove that the proposed design allows a compact and smart power switch realization facing the harshest automotive conditions.

Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip

Clock distribution is an important issue when designing multi processor systems-on-chip on deep sub-micron technology nodes and non-synchronous approaches are becoming popular in this field. This work presents a low-complexity link microarchitecture for mesochronous on-chip communication that enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. With respect to the state of the art, the proposed link architecture stands for its low power and low complexity overheads; moreover it can be easily integrated in a conventional digital design flow since it is implemented by means of standard cells only. Results are presented referring to the link integrated within a multi processor tiled architecture based on a network-on-chip communication backbone on a CMOS 65 nm technology.

Application-Specific Instruction-Set Processor for Retinex-Like Image and Video Processing

This brief presents an application-specific instruction-set processor (ASIP) for real-time Retinex image and video filtering. Design optimizations are addressed at algorithmic and architectural levels, the latter including a dedicated memory structure, an adapted pipeline, bypasses, a custom address generator and special looping structures. Synthesized in CMOS technology, the ASIP stands for its better energy-flexibility tradeoff versus reference ASIC and digital signal processing Retinex implementations.

A Flexible LED Driver for Automotive Lighting Applications: IC Design and Experimental Characterization

This letter presents a smart driver for LEDs, particularly for automotive lighting applications, which avoid ringing and overshoot phenomena. To this aim, advanced Soft Start and Current Slope Control techniques are integrated on-chip. This letter discusses the driver design integrating in high voltage CMOS technology, the digital circuitry for programming and electronic control units interfacing, and the power devices up to 10 W. Experimental characterizations with LEDs of different power levels and with different types of connections are showed. The smart driver sustains automotive temperature and voltage requirements; moreover it has high power efficiency, it is programmable, and can be configured to work as a linear regulator (for low current LEDs) or in switch mode (for higher power LEDs).

Algorithmic and architectural design for real-time and power-efficient Retinex image/video processing

This paper presents novel algorithmic and architectural solutions for real-time and power-efficient enhancement of images and video sequences. A programmable class of Retinex-like filters, based on the separation of the illumination and reflectance components, is proposed. The dynamic range of the input image is controlled by applying a suitable non-linear function to the illumination, while the details are enhanced by processing the reflectance. An innovative spatially recursive rational filter is used to estimate the illumination. Moreover, to improve the visual quality results of two-branch Retinex operators when applied to videos, a novel three-branch technique is proposed which exploits both spatial and temporal filtering. Real-time implementation is obtained by designing an Application Specific Instruction-set Processor (ASIP). Optimizations are addressed at algorithmic and architectural levels. The former involves arithmetic accuracy definition and linearization of non-linear operators; the latter includes customized instruction set, dedicated memory structure, adapted pipeline, bypasses, custom address generator, and special looping structures. The ASIP is synthesized in standard-cells CMOS technology and its performances are compared to known Digital signal processor (DSP) implementations of real-time Retinex filters. As a result of the comparison, the proposed algorithmic/architectural design outperforms state-of-art Retinex-like operators achieving the best trade-off between power consumption, flexibility, and visual quality.

Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding

Real-time and high-quality video coding is gaining a wide interest in the research and industrial community for different applications. H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, high-definition TV and DVD-based systems, which require to sustain up to tens of Mbits/s. To that purpose this paper proposes optimized architectures for H.264/AVC most critical tasks, Motion estimation and context adaptive binary arithmetic coding. Post synthesis results on sub-micron CMOS standard-cells technologies show that the proposed architectures can actually process in real-time 720x480 video sequences at 30 frames/s and grant more than 50Mbits/s. The achieved circuit complexity and power consumption budgets are suitable for their integration in complex VLSI multimedia systems based either on AHB bus centric on-chip communication system or on novel Network-on-Chip (NoC) infrastructures for MPSoC (Multi-Processor System on Chip).