Eugene R. Atwood

Analog Fault Simulation: Need it? No. It is already done

Analog design requires simulation comprehending detailed and accurate semiconductor process knowledge in order to produce designs which will (one hopes) meet narrowly defined specifications. QED The fault simulation is already done! ((Quod erat demonstrandum = which was to be demonstrated.) for those, like me, wondering what the latin acronym means...) Model-to-hardware correlation is a requirement for design success. The simulation of analog devices occurs in the same manner as digital devices for reasonably small counts of devices. It is only when large numbers of digital devices are connected together that the expedient of switch based stuck fault testing is applied. Is there yet an ‘analog’ to the digital modeling process? Should there be? Simulating gross faults, like stuck fault behavior, using switch based methods is pointless when applied to complex analog circuits. Clearly the simulated defective analog behavior will deviate from the expected unless aliasing is possible. Murphy will ensure its untimely arrival. For combined analog functions ‘logic depth’ grows much more rapidly than digital logic having similar transistor counts, particularly if the combined analog devices have continuous response ranges. What does coverage mean in this environment? How is a passing range of values defined?

A test methodology to support an ASEM MCM foundry

MCM testing can be challenging enough when the chip, substrate, and MCM design are within the control of the same company. In the foundry environment, however, even more robust strategies must be adopted. In this paper a test methodology is described which consolidates the various MCM test stages to form a flexible, low-cost, quick turn-around-time test flow.

Managing process variance in analog designs

Methods to manage the effect of process normal and process variance on analog circuit designs have driven significant invention within the analog design community. Has test kept up with ensuring outgoing quality? The application of digital algorithms, which control various types of trimming devices, has enabled built in self-calibration (BISC) of sophisticated analog functions. High speed serial applications, phase locked loops, analog-to-digital converters, low voltage amplifiers and digital radios all benefit from improvements to their respective signal-to-noise ratios. In the very large scale integrated digital design space, embedded analog monitors are used to support optimization of power-performance metrics by adjustments to clock tree timing, power supply domain voltage adjustments and circuit redundancy. Memories benefit from redundancy and are a true mixed signal analog design, relying on sophisticated sense amplifiers. All integrated circuits are based on analog circuit behaviors influenced by process variance. Analog functions continue to be specification tested, which has its own unique coverage issues, but what about the supporting digital circuitry, analog calibration circuitry and redundant logic circuitry? “Who is watching the watchers?” How often is calibration circuitry used? Calibration and redundant circuitry are subject to aging and reliability issues. What needs to be considered in managing these issues? Can useful process feedback information be developed from manufacturing test use of BISC results? Are some calibrations required to be traceable to a standard? How is the relationship managed between analog designers and manufacturing test? Are test access port standards exploited or are ad-hoc access methods used? What can be done to improve the engineering design automation (EDA) environment? Panelists will be asked to present a specific application (case study.) The case study should describe the EDA environment, design/test development flow, the method of BISC or other tuning application and finally manufacturing test application and coverage. Panelists will each be asked to provide an “axiom” intended to provide guidance to engineers working in the area of calibration.

Test and Burn-in Sockets

This chapter addresses the use of area-array socket technology during test and burn-in at the module level. Single chip and multichip modules (SCM, MCM) and their corresponding socket form factors are described ranging from small chip scale packages (CSP) having micro ball grid arrays (MBGA) to very large land grid arrays (LGA) having in excess of 5000 I/Os [1]. Module sizes correspondingly range from tens of millimeters to over one hundred millimeters. Module frequencies of operation range from typical values of approximately 60 MHz for low-end digital applications to multi-gigahertz rf applications. Operating frequency is a primary socket design factor since it has a significant influence on the module contacting method.

Wafer-Level Test

Successful development and manufacture of semiconductor components is highly dependent on test verification at several critical steps throughout the process and at multiple levels of packaging. An effective test methodology spans a broad range of products, diverse test systems and product-handling equipment, and encompasses several test techniques. A reliable and cost-effective product contacting method is a key requirement for all of these test techniques to be successful.