Eugene R. Worley

Distributed gate ESD network architecture for inter-power domain signals

This paper examines the issue of transmitting signals between circuits of different power domains within an IC and the ESD sensitivity of the receiving logics oxide in advanced processes. It is also shown that the ESD stress voltage appearing across a receiving gates oxide can be distributed among several inverters. Also, design of interface attenuation networks that allow large voltage drops between domains for both CDM and HBM tests will be examined.

Optimization of input protection diode for high-speed applications☆

Optimization of input protection diodes for high-speed applications including RF and Internet receivers is examined. The key parameters used to rate the diodes are the RC time constant and the failure point defined by HBM failure voltage per unit of capacitance. Minimizing the RC time constant for stripe diodes includes looking at tapered metal, wide ground stripes, slot contacts, background doping, and the length of the stripes. Maximizing the failure point includes looking at tapered metal, contacts, and proximity effects.

High current characteristics of devices in a 0.18 /spl mu/m CMOS technology

ESD protection networks can involve several different types of devices and associated interconnect. This paper examines the high current performance of several devices that can be found in the I/O cells of a 0.18 micron CMOS technology. Devices characterized include NFETs with and without N well drain resistors including segmented resistors, N well resistors, N channel field snap-back devices, PFETs, and diodes. Also examined is the performance of metal, contacts, and vias. Diode interconnect is also analyzed with respect to failure point and parasitic resistance.