Eun-cheol Kim

A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes

A 116.7-mm/sup 2/ NAND flash memory having two modes, 1-Gb multilevel program cell (MLC) and high-performance 512-Mb single-level program cell (SLC) modes, is fabricated with a 0.15-/spl mu/m CMOS technology. Utilizing simultaneous operation of four independent banks, the device achieves 1.6 and 6.9 MB/s program throughputs for MLC and SLC modes, respectively. The two-step bitline setup scheme suppresses the peak current below 60 mA. The wordline ramping technique avoids program disturbance. The SLC mode uses the 0.5-V incremental step pulse and self-boosting program inhibit scheme to achieve high program performance, and the MLC mode uses 0.15-V incremental step pulse and local self-boosting program inhibit scheme to tightly control the cell threshold voltage V/sub th/ distributions. With the small wordline and bitline pitches of 0.3-/spl mu/m and 0.36-/spl mu/m, respectively, the cell V/sub t/h shift due to the floating gate coupling is about 0.2 V. The read margins between adjacent two program states are optimized resulting in the nonuniform cell V/sub t/h distribution for MLC mode.

A 3.3 V 1 Gb multi-level NAND flash memory with non-uniform threshold voltage distribution

A 1 Gb NAND flash memory with 2b per cell uses 0.15 /spl mu/m CMOS and achieves simultaneous operation of 4 independent banks with 1.6 GMB/s program throughput. Fusing enables changing to 512 Mb 1b-per-cell NAND flash memory. Wordline ramping minimizes noise and peak current. Disturb mechanisms and noise related V/sub TH/ distribution shifts are minimized to improve read margins.