Jung-Dal Choi

Effects of floating-gate interference on NAND flash memory cell operation

Introduced the concept of floating-gate interference in flash memory cells for the first time. The floating-gate interference causes V/sub T/ shift of a cell proportional to the V/sub T/ change of the adjacent cells. It results from capacitive coupling via parasitic capacitors around the floating gate. The coupling ratio defined in the previous works should be modified to include the floating-gate interference. In a 0.12-/spl mu/m design-rule NAND flash cell, the floating-gate interference corresponds to about 0.2 V shift in multilevel cell operation. Furthermore, the adjacent word-line voltages affect the programming speed via parasitic capacitors.

A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes

A 116.7-mm/sup 2/ NAND flash memory having two modes, 1-Gb multilevel program cell (MLC) and high-performance 512-Mb single-level program cell (SLC) modes, is fabricated with a 0.15-/spl mu/m CMOS technology. Utilizing simultaneous operation of four independent banks, the device achieves 1.6 and 6.9 MB/s program throughputs for MLC and SLC modes, respectively. The two-step bitline setup scheme suppresses the peak current below 60 mA. The wordline ramping technique avoids program disturbance. The SLC mode uses the 0.5-V incremental step pulse and self-boosting program inhibit scheme to achieve high program performance, and the MLC mode uses 0.15-V incremental step pulse and local self-boosting program inhibit scheme to tightly control the cell threshold voltage V/sub th/ distributions. With the small wordline and bitline pitches of 0.3-/spl mu/m and 0.36-/spl mu/m, respectively, the cell V/sub t/h shift due to the floating gate coupling is about 0.2 V. The read margins between adjacent two program states are optimized resulting in the nonuniform cell V/sub t/h distribution for MLC mode.

A 3.3 V 1 Gb multi-level NAND flash memory with non-uniform threshold voltage distribution

A 1 Gb NAND flash memory with 2b per cell uses 0.15 /spl mu/m CMOS and achieves simultaneous operation of 4 independent banks with 1.6 GMB/s program throughput. Fusing enables changing to 512 Mb 1b-per-cell NAND flash memory. Wordline ramping minimizes noise and peak current. Disturb mechanisms and noise related V/sub TH/ distribution shifts are minimized to improve read margins.

A novel NAND-type MONOS memory using 63nm process technology for multi-gigabit flash EEPROMs

A NAND-type MONOS device has been successfully developed by breakthrough technologies including optimized cell structures and integration schemes providing favorable memory cell structures and peripheral circuits. In this study, optimized TANOS (TaN-Al2O 3-nitride-oxide- silicon) cells integrated using 63nm NAND flash technology showed high performance compatible to floating-gate (FG) cell. The newly-developed TANOS-NAND flash technology proved to be a promising candidate to replace FG memory beyond 50nm technology

Future Outlook of NAND Flash Technology for 40nm Node and Beyond

The NAND flash memory occupied 40% of the total flash memory market with an annual growth rate of 70% in 2004, while NOR flash achieved only more modest growth rate of 30%. It is expected that NAND flash will surpass the market share of NOR flash in the flash market for the first time in 2005. From the viewpoint of market trend, NAND flash will be more popular in future because of more diversified applications such as NHDD (NAND-HDD) and sub-notebook PC storage. In this paper, we review the critical barriers in further scaling down NAND flash to 40nm technology node and beyond. Then, breakthrough technologies are addressed to overcome the barriers. In addition, issues in performance and reliability of the high density NAND flash are discussed

A non-linear ReRAM cell with sub-1μA ultralow operating current for high density vertical resistive memory (VRRAM)

A non-linear RRAM cell with sub-1μA ultralow operating current has been successfully fabricated for high density vertical ReRAM (VRRAM) applications. A uniform and reproducible low power resistive switching was achieved by engineering transition metal oxides and imposing thin insulating layer as a tunnel barrier. The non-linear I-V characteristics ensure the possible incorporation of RRAM cell into high density cross-type array structure including VRRAM. By varying the current compliance, a multi level switching behavior was obtained. Moreover, excellent endurance of more than 107 cycles without read disturbance for up to 104 seconds was demonstrated.

8 Gb MLC (multi-level cell) NAND flash memory using 63 nm process technology

For the first time, 8 Gb multi-level cell (MLC) NAND flash memory with 63 nm design rule is developed for mass storage applications. Its unit cell size is 0.0164 /spl mu/m/sup 2/, the smallest ever reported. ArF lithography with off-axis illumination (OAI) was employed for critical layers. In addition, self-aligned floating poly-silicon gate (SAP), tungsten gate with an optimized re-oxidation process, oxide spacer and tungsten bit-line (BL) with low resistance were implemented.

Highly Manufacturable 32Gb Multi -- Level NAND Flash Memory with 0.0098 μm 2 Cell Size using TANOS(Si - Oxide - Al2O3 - TaN) Cell Technology

A highly manufacturable 32Gb multi-level NAND flash memory with 0.0098 μm2 cell size using 40nm TANOS cell technologies has been successfully developed for the first time. The main key technologies of 40nm 32Gb NAND flash are advanced high N.A immersion photolithography with off-axis illumination system, advanced blocking oxide of the TANOS cell, and PVD tungsten and flowable oxide for bit line

Highly scalable NAND flash memory with robust immunity to program disturbance using symmetric inversion-type source and drain structure

The symmetric inversion-type S/D structure has been employed for achieving available program disturbance for scaled NAND flash memory beyond sub-40 nm node. The inversion S/D structure enables the channel doping to be reduced due to non-existence of n-lateral diffusion and it suppresses charge sharing between program-inhibit channels, resulting in superior program disturbance. Moreover, the cells show better current drivability in the technology node less than 50 nm by more successful working of gate fringing field with smaller word-line gap, compared to those with the n-diffused S/D junction.

High-performance 1-Gb-NAND flash memory with 0.12-/spl mu/m technology

A 1.8-V, 1-Gb NAND flash memory is fabricated with 0.12-/spl mu/m CMOS STI process technology. For higher integration, a 32-cell NAND structure, which enables row decoder layout in one block pitch, is applied for the first time. Resulting cell and die sizes are 0.076 /spl mu/m/sup 2/ and 129.6 mm/sup 2/, respectively. A pseudo-4-phase charge pump circuit can generate up to 20 V even under the supply voltage of 1.6 V. A newly applied cache program function and expanded page size of (2 k + 64) byte lead to program throughput of 7 MB/s. The page copy-back function is provided for on-chip garbage collection. The read throughput of 27 MB/s is achieved by simply expanding I/O width and page size. A measured disturbance free-window of 3.5 V at 1.5 V-V/sub DD/ is obtained.