Eun Dong Kim

Damage Relaxation Pre-Activation Anneal in Al-Implanted SiC

The effect of pre-activation annealing on the final surface morphology f the Al implanted 4H-SiC has been investigated using atomic force microscopy (AFM). The implanted SiC was annealed in dual steps; the pre-activation annealing which was done at 1100~1500 C earlier, and the activation one subsequently done at 1600 C. The implanted SiC showed the well-developed macrosteps after the activation annealing, while the unimplanted ones showed smoother surfaces. The pre-activation annealing at 1400 C was very effective to reduce the macrostep formation during the activation annealing. The surface damage induced from the ion implantation ha s been relaxed during the pre-activation annealing, which seemed to suppress the macrostep f ormation on the surface of SiC.

Reduction of elastic strains in directly-bonded silicon structures

The elastically strained state of the interface in directly-bonded silicon structures has been studied by x-ray diffraction topography and IR spectrometry. The pattern of the contrast observed in the x-ray topographs and the intensity oscillations in the IR spectra indicate a periodic strain distribution caused by the long-period surface microroughness on the plates to be bonded. The local microroughness did not exceed 2 Å, and it did not noticeably affect the interface structure. Two types of the structure were subjected to a comparative analysis, (i) with a smooth interface prepared by standard direct-bonding technology, and (ii) with an interface displaying a regular relief. The strain level in type-II structures was found to be lower by more than an order of magnitude. A model is proposed to account for the observed reduction of elastic strains at the bonded sections of the interface in terms of elastic relaxation of the free surfaces in the relief voids through their deflection and displacement.

The Method for Enhancing Nitrogen Doping in 6H-SiC Single Crystals Grown by Sublimation Process: The Effect of Si Addition in SiC Powder Source

The variation of nitrogen doping concentration was systematically investigated with respect to the amount of silicon powder added to the SiC powder for growing n-type 6H-SiC single crystal by the sublimation method. To change intentionally the Si content in the SiC powder, 0wt% to 2wt% of a silicon powder was added to first-thermal treated SiC powder and the mixed powder was treated again at 1800oC for 3 hours to eliminate excess free-metallic silicon. Nitrogen doped 6H-SiC single crystals were grown by using 2nd-thermal treatment SiC powder at fixed N2/(Ar + N2) (3%). The nitrogen doping concentration of 6H-SiC crystals increased with increasing Si content in the SiC powder. In this work, we could identify that the additional silicon powder in SiC powder plays a role in the enhancement of nitrogen doping in 6H-SiC crystals grown by the sublimation method.

Static and dynamic characteristics of the 2.5kV/500A IGCTs

IGCT thyristor has many superior characteristics compared with the GTO thyristor. For example, snubberless turnoff capability, short storage time, high turn-on capability, small turn-off gate charge and low total power loss of the application system containing device and peripheral parts such as anode reactor and snubber capacitance. In these characteristics, particularly turn-off capabilities are much important parameter because applications conditions of conventional GTO thyristor are mainly restricted by the limit of these disadvantages of the GTO thyristor. The basic structure of the GCT thyristor is the same as that of the GTO thyristor. This makes the blocking voltage higher and the controllable on-state current higher. The turn-off characteristic of the GCT is influenced by the minority carrier lifetime and the performance of the gate drive circuit. In this paper, we present turn-off characteristics of the 2.5kV/500A PT(Punch-through) type IGCT as a function of the minority carrier lifetime and variation of the doping profile shape of p-base region. Current overshoot characteristics of the IGCT via the doping profile of the p-base region also present.

Edge Termination Technique for SiC Power Devices

The breakdown characteristics of 4H-SiC power device with the three types of edge termination technique, field limiting ring(FLR), field plate(FP) and junction termination extension(JTE), are investigated. The n-type 4H-SiC wafer with 10μm epi-layer and a doping concentration of 5.4 10 15 /cm 3 is used to simulate the power pn diode with each type of edge termination structure. From the optimized simulation results, the breakdown voltages of pn diode with FLR, FP and JTE termination are 1810V, 1130V and 1000V, respectively. The peak electric field of the FP and JTE termination occurs at the surface and the interface between main junction and JTE region, which yields lower breakdown voltage. Conversely, the peak electric field of FLR termination at the interface between SiC and oxide is lower than that at the junction of the 2 nd ring edge. This means that the breakdown of the FLR termination occurs at the bulk region of the device, so that the breakdown voltage of the FLR termination is higher and stable. The breakdown voltage of the fabricated pn diode with FLR termination is measured 1782V, which is similar to the simulated one. Therefore, in SiC power devices, the FLR structure seems to be suitable for obtaining an ideal breakdown and a practical planar termination technique. Introduction The excellent physical and electrical properties of silicon carbide make it an important device material for high power, high temperature, and high frequency applications [1,2]. Due to its material characteristics, silicon carbide power devices exhibit superior device characteristics than that of the silicon power devices, such as high breakdown voltage, low on-state voltage drop, etc. In the high voltage devices, edge termination technique has an important role for determining the breakdown voltage. In silicon power devices, FLR, FP, and JTE techniques are mostly used to terminate the edge of the devices due to its advantages. The FP structure can be fabricated easily and compatible but hard to obtain high voltage. Even if JTE structure is usually considered as an ideal termination technology, it is virtually hard to optimize because it is so sensitive to the doping concentration of JTE region. The doping concentration is usually controlled by diffusion process in traditional silicon technology. The floating field rings can be formed without an additional processing step during the fabrication of the power pn diode and MOSFET. However, it needs large termination area to obtain high breakdown voltage. In SiC power devices, some of these disadvantages can be eliminated due to the material characteristics of the SiC. In this paper, 4H-SiC pn diode using several edge termination techniques is presented. We simulate and compare the feature of the each termination technique. Especially for the FLR edge termination technique, we simulate to optimize the structure and fabricated pn diodes. The characteristics of the structures are verified by the two-dimensional device simulator ATLAS [3]. Results and Discussion N-type 4H-SiC pn diode with 10μm epi-layer thickness and a doping concentration of 5.4 10 15 /cm 3 is used to simulate the each type of edge termination structure. Figure 1 shows the cross-sectional view of the various termination structures for the simulation. Two floating field rings are basically Materials Science Forum Online: 2004-06-15 ISSN: 1662-9752, Vols. 457-460, pp 1241-1244 doi:10.4028/www.scientific.net/MSF.457-460.1241

Fabrication of high quality SOI bonding materials by modified direct wafer bonding technique

A modified direct bonding technique employing a deposition on a wafer to be bonded of silica coating is proposed for the fabrication of Si-SiO/sub 2/-Si structures. The structural and electrical quality of bonded compositions is studied. Satisfied insulating properties of interfacial SiO/sub 2/ layer are demonstrated. Elastic strain caused by surface morphology in the structures with smooth and artificially grooved interfaces is investigated. The diminution of strain in the grooved structures is semi quantitatively interpreted by a model considering the virtual defects distributed over the interfacial region.

A Study on the Effective Communication Protocol of the Surface Inspection Rail Robot that it can be a Self-checking

The robots that they inspect the rail surface with running above the rail will be a means to replace the existing expensive equipments. This can be very effectively used in the process of construction and maintenance of continuous increased rail industry. Especially, it can detect the small change via the build of database for detecting the state of the rail. And it is possible the continuous management by recording this information. However, these rail robots are attached a number of different rail parts. Thus, if these components are not gonna work, it can occur problems such as stop on the rail or derailed. These issues can be occurred to other train that it runs above the rail. Therefore, it needs the method for ensuring the safety. In this paper, in order to solve these problems, we define the components and performance parts that rail robot should have it. And also, we divide into three groups of devices by analyzing the properties of each of the components. Each of the group was divided according to the calculation processing capability and communication capability. The self-verification of equipments performs with fitting the framework. And they examine its own equipment validation and review whether the operation is enabled or impossible to perform in accordance with the information. In addition, the rail robot continues send the information for the rail status via wireless network with control center. Thus, we propose an efficient communication protocol in consideration of security issues that there may occur in sending process and the scalability of the function side for rail robot.

Numerical Simulation and Optimization for 900V 4H-SiC DiMOSFET fabrication

We report the simulation results of 25µm half cell pitch vertical type 4H-SiC DiMOSFET using the general-purpose device simulator MINIMOS-NT. The best trade-off between breakdown voltage and on-resistance in terms of BFOM is around 19MW/cm2 with a p-well spacing 5µm. The specific on -resistance, RON, sp, simulated with VGS=10V and VDS=1V at room temperature, is around 22.76mWcm2. An 900V breakdown voltage is simulated with ion-implanted edge termination.

Trench Formation on Ion Implanted SiC Surfaces after Thermal Oxidation

The effects of the damage induced during ion implantation on the surface roughening and oxide growth rate were investigated. Using several scheme of doses and acceleration energies, it is found that the amount of the dose predominantly produce damage rather than the acceleration energy, especially near the surface region. It was also found that the damage affects not only the oxide growth rate but also the surface roughening during high temperature annealing. The edge of highly implanted area may have higher doping concentration due to the vicinal side wall effect of the thick oxide mask for ion implantation. It was confirmed by the trench formation after thermal oxide remove.

Co-Formation of Gate Electrode and Ohmic Contacts in SiC Power MOSFETs

The characteristic and possibility of nickel as a gate electrode material instead of polysilicon have been investigated for 4H-SiC power MOSFETs. MOS capacitors were fabricated by oxidizing and subsequently depositing nickel or polysilicon on the thermal oxide layer. In order to investigate the effect of the rapid-thermal-annealing (RTA) on the oxide quality, the MOS capacitors with nickel or polysilicon gate were annealed at 950°C for 90sec. The interface trap densities of the oxide did not vary even after the RTA process, implying the quality of gate oxide was not affected by the RTA. The breakdown voltage of the gate oxides was 44-55V in the as-deposited samples, which was maintained after the high temperature annealing.