Eun-Gu Jung

Implementation of High Performance CAVLC for H.264/AVC Video Codec

Context-based adaptive variable length coding (CAVLC) is entropy coding for H.264/AVC video codec. Since the CAVLC is highly context-adaptive and of a block-based context formation, high coding efficiency is achieved. However, its high complexity causes various difficulties in full-hardware implementation. This paper presents high performance hardware architecture of CAVLC. The proposed architecture is implemented in a FPGA device, and verified by RTL simulations. The implementation results show that the proposed architecture encodes a 4times4 block per 16 clock cycles, and achieves a real-time processing for 1920times1088 frame size with 30-fps video at 100MHz clock speed

High performance asynchronous bus for SoC

It is difficult to use synchronous buses in a system-on-a-chip design due to the increase of wire delay caused by the crosstalk effect and the difficulty of the synchronization caused by the clock-skew problem. The use of an asynchronous bus is an alternative solution for the SoC design method. In this paper, we propose a new high performance asynchronous bus using a return-to-zero data encoding method to get a low latency and a high throughput as well. Simulation results reveal that, by the proposed scheme, the read throughput increases by 17.6%, and the read latency decreases by 12.5% simultaneously.

Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions

In this paper, a novel asynchronous layered interface for a high performance on-chip bus is designed in a Globally Asynchronous Locally Synchronous (GALS) style. The proposed asynchronous layered interface with distributed and modularized control units supports multiple outstanding in-order/out-of-order transactions to achieve high performance. In the layered architecture, extension of an asynchronous layered interface performing complex functions is readily achieved without repeating the implementation of the whole bus interface. Simulations are carried out to measure the performance and power consumption of implemented asynchronous on-chip bus with the proposed asynchronous layered interface. Simulation results demonstrate that throughput of the asynchronous on-chip bus with multiple outstanding out-of-order transactions is increased by 30.9%, while power consumption overhead is 16.1% and area overhead is 56.8%, as compared to the asynchronous on-chip bus with a single outstanding transaction.

Exploration of Power-Delay Trade-Offs with Heterogeneous Adders by Integer Linear Programming.

The performance of arithmetic adders varies widely in their power consumption, delay, and area requirements. To acquire more fine-grained trade-offs in the power-delay trade-off curve of a binary adder, the heterogeneous adder architecture is adopted. In heterogeneous adder architecture, a binary adder is decomposed into sub-adder blocks with different carry propagation schemes and bit-widths. Thus the method allows us to expand the original design space of a specific type of adder into the more fine-grained design space by mixing that of each sub-adder. In this paper, a design for heterogeneous adder through power optimization under delay constraints or delay optimization under power constraints was presented by determining the bit-width of each sub-adder. Also the effectiveness of the proposed method was demonstrated by showing the ratio of the power consumption of heterogeneous adder to that of conventional adder.

Parallel 4/spl times/4 transform architecture based on bit extended arithmetic for H.264/AVC

H.264/AVC, the latest standard for the coding of video signal, utilizes a 4/spl times/4 integer transform to concentrate energy of residual data in a few coefficients. In this paper, a new parallel 4/spl times/4 transform architecture based on bit extended arithmetic is proposed for H.264/AVC. Compared with the existing parallel architecture, the proposed architecture eliminates redundant logic through bit extended arithmetic. Simulation results show that the hardware complexity is decreased by 25% and the data processing rate is increased by 16%.

High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion

In this paper, we propose a high performance asynchronous on-chip bus with multiple issue and in-order/out-of-order completion for a Globally Asynchronous Locally Synchronous (GALS) design. The proposed bus implementation can be characterized with distributed and modularized control units based on a layered architecture to support multiple issue and in-order/out-of-order completion. Simulation results reveal that throughputs of asynchronous on-chip buses with multiple issue and in-order/out-of-order completion increases by 31.3% / 34.3%, while power consumption overhead is only 6.76% / 3.98% respectively, compared to a simple asynchronous on-chip bus with only a single issue feature.

Cost-effective delay-insensitive data transfer mechanism using current-mode multiple valued logic

In this paper, we propose a new data transfer mechanism based on delay-insensitive (DI) data coding with current-mode multiple valued logic (CMMVL). In previous DI data coding, the number of required wires for transferring N-bit data is 2N+1. However, only N+1 wires are needed in our transfer mechanism so it can contribute greatly to reducing the wire cost for designing a large scaled chip. We compare the proposed CMMVL circuit with conventional dual-rail DI encoding to validate its effectiveness through simulation in 0.25 /spl mu/m CMOS technology. In addition to advantage in wire cost, for 32 bit data transfer, simulation results show that the MVL version is superior to the dual-rail version by about 24.9% in the metric of time-power product. We also apply the MVL version to a practical environment such as an asynchronous bus architecture.

Implementation of High Data Rate Stream Parsing with Data Aligning Mechanism

Nowadays the HDTV (high definition television) is growing more and more popular. In many cases a compression of this high quality multimedia data is needed for storing or transmitting purposes. In order to preserve good quality, the compressed stream should have high data rate. It is also common case to combine several such streams, representing different programs, into one single multimedia stream. Here comes the need of high data rate multiplexing and demultiplexing. To operate with high data rate stream, the clock frequency, the word width or both have to be increased. For cost efficient FPGA implementation the wider word width is preferred, which allows smaller in logic and slower in speed FPGA to be used. In this paper the issues following this choice are revealed and a data aligning implementation technique is proposed

Implementation of asynchronous reorder buffer for asynchronous on-chip bus

Asynchronous reorder buffer (ROB) is an important component to support in-order completion of data transactions on an asynchronous on-chip bus with multiple outstanding transactions. In this paper, two asynchronous ROBs are proposed. Based on an asynchronous circular buffer with distributed control, an asynchronous ROB is proposed for asynchronous microprocessors, which solves problems of a conventional asynchronous ROB for asynchronous microprocessors. The same scheme can be used for an asynchronous on-chip bus, but its use generates some redundancy. This redundancy results from differences between two asynchronous ROB operating environments. By eliminating this redundancy, an optimized asynchronous ROB with fully distributed control is proposed for asynchronous on-chip bus. The proposed asynchronous ROB is integrated into an asynchronous on-chip bus and simulations are performed.

High speed JPEG coder based on modularized and pipelined architecture with distributed control

The design of an efficient reusable IP based Extended JPEG encoder is presented in this paper. This encoder uses user-defined quantization and Huffman tables that can be reconfigured at run-time. It has a modularized and pipelined architecture with distributed control for each block. A simple interface makes integration of the modules in various systems simple and straightforward. The design when targeted on FPGA operated at speed of up to 90MHz and when mapped on 0.25μm CMOS process the design can operate at speeds over 450MHz, which is faster than any of the similar JPEG encoder designs reported.