Kyoung-Son Jhang

A Study of Wireless Sensor Network Routing Protocols for Maintenance Access Hatch Condition Surveillance

Maintenance Access Hatches are used to ensure urban safety and aesthetics while facilitating the management of power lines, telecommunication lines, and gas pipes. Such facilities necessitate affordable and effective surveillance. In this paper, we propose a FiCHS (Fixed Cluster head centralized Hierarchical Static clustering) routing protocol that is suitable for underground maintenance hatches using WSN (Wireless Sensor Network) technology. FiCHS is compared with three other protocols, LEACH, LEACH-C, and a simplified LEACH, based on an ns-2 simulation. FiCHS was observed to exhibit the highest levels of power and data transfer efficiency.

A Low Cost and Interactive Rapid Prototyping Platform for Digital System Design Education

In this paper, we describe a cost-effective FPGA-based logic circuit emulation platform. It consists of a hardware engine to emulate the circuits and software for the user interface to drive the emulation and monitor the results. It is a very flexible and powerful design verification platform. Additionally, its economical price makes it possible to assign an FPGA (field programmable gate array) prototyping board to every student. This system provides an interactive verification environment using a communication protocol through bi-directional serial link, like the RS232C. Our system has the potential to meet market demands, especially in the educational field, which requires a low cost and yet powerful verification methods for digital hardware design.

Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions

In this paper, a novel asynchronous layered interface for a high performance on-chip bus is designed in a Globally Asynchronous Locally Synchronous (GALS) style. The proposed asynchronous layered interface with distributed and modularized control units supports multiple outstanding in-order/out-of-order transactions to achieve high performance. In the layered architecture, extension of an asynchronous layered interface performing complex functions is readily achieved without repeating the implementation of the whole bus interface. Simulations are carried out to measure the performance and power consumption of implemented asynchronous on-chip bus with the proposed asynchronous layered interface. Simulation results demonstrate that throughput of the asynchronous on-chip bus with multiple outstanding out-of-order transactions is increased by 30.9%, while power consumption overhead is 16.1% and area overhead is 56.8%, as compared to the asynchronous on-chip bus with a single outstanding transaction.

Automatic Synthesis of Interface Circuits from Simplified IP Interface Protocols and Matching Information

Automatic interface synthesis generates product FSM from interface FSMs of IP. But complicated interface FSM may lead to a very large product FSM which results in large interface circuits. So we propose a simplified interface FSM description scheme where transactions are represented based on transfers and several parameters. In addition, the interface circuit is generated by considering only those transactions which are involved in matching information. By virtue of matching information we could generate the interface circuits which may not be easy to generate with previous methods due to inability to consider the differences in characteristics of interface protocols of IP. Through experiments we observed that our description scheme helps reduce the size of interface circuits and our synthesis method correctly generates the interface circuits between IPs with different characteristics.

Automatic synthesis of interface circuits from simplified IP interface protocols

Most approaches to interface synthesis take two interface FSMs including transactions or burst, derive a product FSM and generate an interface circuit from the product FSM. With these methods, it could be difficult and complicated to describe interface FSM of IP especially when IP has many transactions. Additionally, such descriptions may lead to a very large product FSM which results in large interface circuits. We propose a simplified interface FSM description scheme where transactions are represented based on transfers and several parameters. Since all transactions supported by IP may not be used in the system, the synthesis algorithm is designed to consider only those transactions which are involved in parameter matching. Through experiments we observed that our description scheme helps reduce the size of interface circuits and our synthesis method correctly generates the interface circuits.

TDMA implementation for simultaneous signal acquisition of machine condition in wireless sensor networks

Wireless sensors, installed on machinery, and Time Division Multiple Access (TDMA) transmission make an ideal system for monitoring machine conditions in industrial plants because there is no need for electronic wiring. However, field application of such a system, capable of continuously transmitting data over 100 Hz sample rates, has not been successful so far. In this research, a TDMA network protocol capable of acquiring data from multiple sensors with over 100 Hz sample rates was developed for field application. The protocol was implemented in a single cluster-star topology network and the system was evaluated by node number and transmission distance. The network simulator-2 (ns-2) is used for real field simulation. The cases of non-TDMA and TDMA protocol are compared with four sensor nodes. In the case of a 20-second transmission time, there is little difference between the reception rates of non-TDMA and those of TDMA system. However, the difference was much greater when using a 60-second transmission time.

Analysis of the Single Event Effect of the Science Technology Satellite-3 On-Board Computer under Proton Irradiation

Field Programmable Gate Array(FPGA)s are replacing traditional integrated circuits for space applications due to their lower development cost as well as reconfigurability. However, they are very sensitive to single event upset (SEU) caused by space radiation environment. In order to mitigate the SEU, on-board computer of STSAT-3 employed a triple modular redundancy(TMR) and scrubbing scheme. Experimental results showed that upset threshold energy was improved from 10.6 MeV to 20.3 MeV when the TMR and the scrubbing were applied to the on-board computer. Combining the experimental results with the orbit simulation results, calculated bit-flip rate of on-board computer is 1.23 bit-flips/day assuming in the worst case of STSAT-3 orbit.

Implementation of asynchronous reorder buffer for asynchronous on-chip bus

Asynchronous reorder buffer (ROB) is an important component to support in-order completion of data transactions on an asynchronous on-chip bus with multiple outstanding transactions. In this paper, two asynchronous ROBs are proposed. Based on an asynchronous circular buffer with distributed control, an asynchronous ROB is proposed for asynchronous microprocessors, which solves problems of a conventional asynchronous ROB for asynchronous microprocessors. The same scheme can be used for an asynchronous on-chip bus, but its use generates some redundancy. This redundancy results from differences between two asynchronous ROB operating environments. By eliminating this redundancy, an optimized asynchronous ROB with fully distributed control is proposed for asynchronous on-chip bus. The proposed asynchronous ROB is integrated into an asynchronous on-chip bus and simulations are performed.

Self-timed interconnect with layered interface based on distributed and modularized control for multimedia socs

In this paper, a high performance asynchronous on-chip bus designed in a Globally Asynchronous Locally Synchronous (GALS) style is proposed. The asynchronous on-chip bus is capable of handling multiple outstanding transactions and in-order completion to achieve a high performance, which is implemented with distributed and modularized control unit in a layered interface. The architecture of asynchronous on-chip bus is discussed and implemented for simulations. Simulation results show that throughput of the proposed asynchronous on-chip bus with multiple outstanding transactions and in-order transaction completion is increased by 31.3%, while power consumption overhead is only 6.76%, as compared to an asynchronous on-chip bus with a single outstanding transaction.

A Wrapper Design Methodology Based On IPCs

Reusing IPs requires interface protocol related tasks such as writing test benches and designing interface protocol conversion circuits, e.g. wrappers for IPs. The results of those tasks usually include IPC(interface protocol component)s for the corresponding IPs, similar to bus protocol components of the bus functional models. This paper proposes a methodology for the interface circuit design using synthesizable In that can be re-used. IPC recognizes or executes transactions over the given interface ports. So we present a transaction-oriented interface protocol description language, and a method to convert the description into an IPC in synthesizable VHDL code. With experiments, we show that the interface design using IPC does not cause significant area overhead compared with the interface design without IPC. The proposed IPC-based approach can be employed to reduce the interface design time since the designers can reuse IPCs without understanding the detailed interface protocols.