Eun Seung Jung

Performance evaluation of InGaAs, Si, and Ge nFinFETs based on coupled 3D drift-diffusion/multisubband boltzmann transport equations solver

This paper presents a simulation study of InGaAs, Si, and Ge nFinFETs by solving the coupled drift-diffusion (DD) and the multisubband Boltzmann transport equation (MSBTE) in 3D domains. The effects of the quasi-ballistic transport, source/drain contact resistances, and band-to-band tunneling (BTBT) on the device performance are studied.

Impact of TSV proximity on 45nm CMOS devices in wafer level

Impacts of through-silicon via (TSV) proximity on various 45nm CMOS devices are evaluated in wafer level. Cu-filled TSVs with 6um (dia.) × 55um (height) were formed using ‘via middle’ process. After finishing BEOL module process, electrical measurement was conducted using unthinned wafers. Mostly the device performance change due to TSV is observed in less than 2um distance but the change is less than 2% in maximum. Also discrepancy between theory and real data on TSV impact was identified.

1/2-inch 7.2MPixel CMOS Image Sensor with 2.25/spl mu/m Pixels Using 4-Shared Pixel Structure for Pixel-Level Summation

A 1/2-inch 7.2Mpixel CMOS image sensor with 2.25mum pixels employs a 4-shared pixel structure with pixel-level charge summation. It achieves a 57% fill factor, full well capacity of 14ke- with 41dB maximum SNR at full resolution, 8e-random noise, 15ke-/lux-s sensitivity, and a 3dB increment in SNR for pixel-level charge summation and sub-sampling operation. A 0.13mum Cu process is used

Considerations on highly scalable and easily stackable phase change memory cell array for low-cost and high-performance applications

Needs for the performance improvement of memory subsystem in big data and clouding computing era begin to open new markets for emerging memories such as phase change memory, spin-torque-transfer magnetic memory, and metal oxide memory. To fulfill these needs, a cost-effective and high-speed phase change memory cell scheme was introduced at 19nm technology node, which is directly scalable down to 1y or 1z nm nodes and can be extendable to stacked array for higher density. Here, key technologies such as self-aligned cell patterning and vertical poly-Si diode switch on metal word line were adopted. In addition, damascene Ge-Sb-Te technologies were optimized to improve programming speed and to show excellent cell performances.

Multiple input multiple output controller design to match chamber performance in plasma etching for semiconductor manufacturing

In semiconductor manufacturing, multiple chambers utilized for the same process step often experience performance variation. This chamber to chamber performance variation has affected the yield of wafers, but there are no standard procedures to reduce them in semiconductor manufacturing. This paper introduces chamber matching in plasma etching as one of the core issues in semiconductor manufacturing and suggests a step-by-step procedure to address chamber matching issues. A brief review of two approaches, fault detection and classification and equipment control, is given and a step-by-step procedure of the equipment control approach is introduced. To design a multiple input-multiple output controller, a decomposed etch rate map makes it possible to analyze etch rate performance between chambers and to define controlled variables. Optimum variable selection techniques, such as singular value analysis and relative gain array methods, and dynamic optimization with constraints are suggested in this paper. In ...

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Transistor scaling with the CMOS technology advancement results in <i>f</i> _max saturation in contrast to <i>fT</i> improvement. Effective improvement methods for such saturated <i>f</i> _max are presented to the transistors fabricated by 45- and 65-nm low standby power CMOS technology. The primary parameters investigated are <i>V</i> _th optimization through adjusting the channel implantation and <i>R</i> _sub control through adjusting the active to substrate contact spacing. It is demonstrated that <i>V</i> _th optimization and <i>R</i> _sub control result in more than 20% and 10% improvements for <i>f</i> _max, respectively.

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Transistor scaling with CMOS technology evolution results in <i>f</i> _max saturation in contrast to <i>fT</i> improvement. This letter presents effective improvement methods for such saturated <i>f</i> _max in the transistors fabricated by 45-nm low-standby-power CMOS technology. The primary parameter investigated is the gate layout structure through changing the gate interconnects into several folded structures. It is demonstrated that we can achieve <i>f</i> _max of above 500 GHz and <i>f</i> _max/<i>fT</i> ratio of 2.9 in the transistors through applying the proposed gate layout structures. Such high <i>f</i> _max results from the effective reduction in the gate resistance.

and Substrate Resistance Control for RF Performance Improvement in MOSFETs

A novel compact model is developed by coupling comprehensive physical equations from electrical, thermal and phase-transition domains in order to capture their correlations that exist in GeSeTe (GST) device physics. Several non-ideal effects during GST-based memory cell operations have been studied with particular focus on cell Read/Write margins and reliability issues. Finally, large-scale 3-D cross-point memory array circuits have been simulated with developed physics-based models to further explore the design constraints.

Effective Gate Layout Methods for RF Performance Enhancement in MOSFETs

A comprehensive compact modeling framework coupling quantum transport with magnetic dynamics has been developed for state-of-the-art and emerging STT-MRAMs. After validation with numerical simulation and experimental results, various transistor-MRAM cell architectures have been studied for their performance and variability. SOT-assisted MRAMs are found to have significant improvement on Erase time over conventional STT-MRAMs.

Multi-domain compact modeling for GeSbTe-based memory and selector devices and simulation for large-scale 3-D cross-point memory arrays

As chamber conditions gradually change with wafer processing, periodic wet cleaning is an inevitable event in semiconductor manufacturing. Since the chamber conditions are initialized during the wet cleaning, a chamber conditioning process called chamber seasoning follows the wet cleaning step. In this paper, a systematic procedure to optimize chamber seasoning for plasma etching is proposed, and the effectiveness is demonstrated in a semiconductor manufacturing environment. In order to quantitatively analyze plasma conditions for chamber seasoning and to achieve the optimum conditions objectively, a normalization technique for optical emission spectroscopy called a self-background normalization technique and a computational optimization process is suggested. By applying the optimized chamber seasoning conditions, a plasma reactor which is suffering from a serious etch rate drift after wet cleaning returns to a production ready status. Also, the etch rate of Si, which is an index for production readiness, is perfectly matched to 37.8 A/s for production. Hopefully, the proposed methodology in this paper will be disseminated to semiconductor manufacturers who experience similar issues after wet cleaning.