Kangwook Park

Direct parameter extraction of SiGe HBTs for the VBIC bipolar compact model

An improved direct parameter extraction method of SiGe heterojunction bipolar transistors (HBTs) for the vertical bipolar intercompany (VBIC)-type hybrid-/spl pi/ model is developed. All the equivalent circuit elements are extracted analytically from S-parameter data only and without any numerical optimization. The proposed technique of the parameter extraction, differing from the previous ones, focuses on correcting the pad de-embedding error for an accurate and invariant extraction of intrinsic base resistance (R/sub bi/), formulating a new parasitic substrate network, and improving the extraction procedure of transconductance (g/sub m/), dynamic base-emitter resistance (r/sub /spl pi//), and base-emitter capacitance (C/sub /spl pi//) using the accurately extracted R/sub bi/. The extracted parameters are frequency-independent and reliable due to elimination of any de-embedding errors. The agreements between the measured and model-calculated data are excellent in the frequency range of 0.2-10.2 GHz over a wide range of bias points. Therefore, we believe that the proposed extraction method is a simple and reliable routine applicable to the optimization of transistor design, process control, and the improvement of VBIC compact model, especially for SiGe HBTs.

Impact of TSV proximity on 45nm CMOS devices in wafer level

Impacts of through-silicon via (TSV) proximity on various 45nm CMOS devices are evaluated in wafer level. Cu-filled TSVs with 6um (dia.) × 55um (height) were formed using ‘via middle’ process. After finishing BEOL module process, electrical measurement was conducted using unthinned wafers. Mostly the device performance change due to TSV is observed in less than 2um distance but the change is less than 2% in maximum. Also discrepancy between theory and real data on TSV impact was identified.

Improved VBIC model for SiGe HBTs with an unified model of heterojunction barrier effects

An improved bipolar transistor model considering heterojunction barrier effect (HBE) in SiGe double heterojunction bipolar transistors is developed. The effect of barrier formation due to high level injection, which is related to the rapid degradations of the dc current gain (/spl beta/) and cutoff frequency (f/sub T/), is carefully investigated and analyzed. As the collector current becomes high, the conduction band barrier is induced and increased. It causes the saturation of collector current (J/sub C/) due to the blocking of carrier transport, the sharp increase of base transit time (/spl tau//sub B/) due to the additional charge storage, the increase of base current (J/sub B/) due to the increased recombination, and the decrease of intrinsic base resistance (R/sub bi/) due to the increased charge and base pushout. Those phenomena are included into a vertical bipolar intercompany model (VBIC) compact model by employing a unified model of the HBE on J/sub C/, J/sub B/, /spl tau//sub B/, and R/sub bi/. Furthermore, portions of /spl tau//sub B/ and R/sub bi/ from the Kirk effect itself are modeled according to the high current model description and the new formulation of widened base, respectively. A full extraction of parameters has been performed and the modified VBIC model is applied. The modeling accuracy is significantly improved at the high current region for the dc and RF characteristics.

RF Model of BEOL Vertical Natural Capacitor (VNCAP) Fabricated by 45-nm RF CMOS Technology and Its Verification

A radio-frequency equivalent circuit model for the symmetric vertical natural capacitor (VNCAP) in a 45 nm low-standby-power CMOS process is presented. The average effective capacitance density of 2.24 fF/ mum2 is obtained from VNCAPs of 1 times (M1 - M5) + 2 times (M6 - M7) metal-layer configuration after the open-short de-embedding procedure. The proposed model consists of main series capacitance network and lossy substrate network. The accuracy of the VNCAP model is verified S-parameters, effective capacitance Ceff, and quality factor (Q) up to 15 GHz. The proposed model can accurately describe the frequency characteristics of S-parameters, Ceff, and Q-factor up to 15 GHz for VNCAPs with different widths and lengths.

Effects of Parasitic Capacitance, External Resistance, and Local Stress on the RF Performance of the Transistors Fabricated by Standard 65-nm CMOS Technologies

Effects of parasitic capacitance, external resistance, and local stress on the radio-frequency (RF) performance of the transistors fabricated by 65-nm CMOS technology have been investigated. The effect of parasitic capacitance, particularly Cgb, becomes significant due to the reduced spacing between the gate and the substrate contact (SC) in proportion to scaling down. Current drivability (Idsat) per unit width has been improved through introduction of mobility enhancement techniques. The influence of external resistance becomes more pronounced for large-dimensional RF transistors due to severe IR drop. Such improved current drivability and large external resistance is responsible for dc performance (gm) degradation and, eventually, cutoff frequency (fT) degradation. Local stress effects associated with silicon nitride capping layer and STI stress have been investigated. fT is largely affected by local stress change, i.e., gm degradation at minimal gate poly (GP) pitch and gate-to-active spacing, fT is dominated by increased parasitic capacitance (Cgb) with increasing GP pitch and gate-to-active spacing. Above 10% improvement in fT has been observed through layout optimization for Cgb reduction by increasing the transistor active-to-SC spacing.

Characterization and Modeling of RF-Performance

The fluctuation of RF performance (particularly for f_T: cutoff frequency) in the transistors fabricated by 90-nm CMOS technology has been investigated. The modeling for f_T fluctuation is well fitted with the measurement data within approximately 1% error. Low-V_t transistors (fabricated by lower doping concentration in the channel) show higher f_T fluctuation than normal transistors. Such a higher f_T fluctuation results from C_gg (total gate capacitance) variation rather than g_m variation. More detailed analysis shows that C_gs + C_gb (charges in the channel and the bulk) are predominant factors over C_gd (charges in LDD/halo region) to determine C_gg fluctuation.

(f_{T})

Cut-off frequency (f_T) of 300 GHz and 230 GHz for NMOS and PMOS is demonstrated for transistors with a gate length of 35 nm fabricated by 45 nm standard CMOS technology. Current gain (H₂₁) and noise (flicker and thermal) is improved with scaling down technology. Power gain (G_u) increase is slow down and even saturated at 45 nm as technology advances. Such saturation in power gain is attributed to rapid increase in g_ds (drain conductance). Additional efforts are required to reduce g_ds for continuous improvement in power gain with the scaling. V_th optimization can be one of options to achieve better g_ds.

Fluctuation in MOSFETs

Transistor scaling with the CMOS technology advancement results in <i>f</i> _max saturation in contrast to <i>fT</i> improvement. Effective improvement methods for such saturated <i>f</i> _max are presented to the transistors fabricated by 45- and 65-nm low standby power CMOS technology. The primary parameters investigated are <i>V</i> _th optimization through adjusting the channel implantation and <i>R</i> _sub control through adjusting the active to substrate contact spacing. It is demonstrated that <i>V</i> _th optimization and <i>R</i> _sub control result in more than 20% and 10% improvements for <i>f</i> _max, respectively.

Effect of technology scaling on RF performance of the transistors fabricated by standard CMOS technology

Transistor scaling with CMOS technology evolution results in <i>f</i> _max saturation in contrast to <i>fT</i> improvement. This letter presents effective improvement methods for such saturated <i>f</i> _max in the transistors fabricated by 45-nm low-standby-power CMOS technology. The primary parameter investigated is the gate layout structure through changing the gate interconnects into several folded structures. It is demonstrated that we can achieve <i>f</i> _max of above 500 GHz and <i>f</i> _max/<i>fT</i> ratio of 2.9 in the transistors through applying the proposed gate layout structures. Such high <i>f</i> _max results from the effective reduction in the gate resistance.